Ultra low power 12-Bit SAR ADC for wireless sensing applications

Raja Hari Gudlavalleti, S. C. Bose
{"title":"Ultra low power 12-Bit SAR ADC for wireless sensing applications","authors":"Raja Hari Gudlavalleti, S. C. Bose","doi":"10.1109/VLSI-SATA.2016.7593060","DOIUrl":null,"url":null,"abstract":"This paper presents a 12-bit SA-ADC for portable low power wireless sensor systems. The proposed SA-ADC operates for rail-to-rail input range and achieves low power consumption. Split capacitor array based DAC and a novel charge-integration based dynamic comparator are used for low power consumption of the ADC. Measured DNL and INL are -0.59/0.67 LSB and -1.2/1.33 LSB respectively. At sampling rate of 100-kS/s with 1.8-V supply, the ADC consumes only 2-μW power and achieves a SNDR of 64.42-dB, SFDR of 71.2-dB resulting in an FoM of 14-fJ/Conversion-step. The ADC core occupies an area of 0.238-mm2 and is fabricated in AMS 0.35-μm CMOS technology.","PeriodicalId":328401,"journal":{"name":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-SATA.2016.7593060","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

Abstract

This paper presents a 12-bit SA-ADC for portable low power wireless sensor systems. The proposed SA-ADC operates for rail-to-rail input range and achieves low power consumption. Split capacitor array based DAC and a novel charge-integration based dynamic comparator are used for low power consumption of the ADC. Measured DNL and INL are -0.59/0.67 LSB and -1.2/1.33 LSB respectively. At sampling rate of 100-kS/s with 1.8-V supply, the ADC consumes only 2-μW power and achieves a SNDR of 64.42-dB, SFDR of 71.2-dB resulting in an FoM of 14-fJ/Conversion-step. The ADC core occupies an area of 0.238-mm2 and is fabricated in AMS 0.35-μm CMOS technology.
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用于无线传感应用的超低功耗12位SAR ADC
提出了一种用于便携式低功耗无线传感器系统的12位SA-ADC。所提出的SA-ADC工作在轨对轨输入范围内,实现了低功耗。为了降低ADC的功耗,采用了一种基于分裂电容阵列的DAC和一种新颖的基于电荷集成的动态比较器。测得DNL和INL分别为-0.59/0.67 LSB和-1.2/1.33 LSB。在采样率为100-kS/s,电源为1.8 v时,ADC功耗仅为2 μ w, SNDR为64.42 db, SFDR为71.2 db, FoM为14-fJ/转换步长。ADC核心面积为0.238 mm2,采用AMS 0.35 μm CMOS技术制造。
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