A model for testing reliable VLSI routing architectures

C. Stivaros
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引用次数: 1

Abstract

Presents a model for testing the reliability of VLSI interconnection topologies. It is assumed that terminals on an electronic board may fail to operate independently and with manufacturer-supplied probabilities. The authors are concerned with the ability of the operating terminals to communicate in order to carry out their tasks. The two schemes examined are the channel and match-box routing topologies which are translated to their underlying probabilistic graphs as an illustration of the applicability of combinatorial optimization techniques. Their optimality is tested under all possible failure vectors.<>
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一个测试可靠VLSI路由架构的模型
提出了一种测试超大规模集成电路互连拓扑可靠性的模型。假设电子板上的端子可能无法独立运行,并且具有制造商提供的概率。作者关注的是操作终端为了完成任务而进行通信的能力。研究的两种方案是信道和火柴盒路由拓扑,它们被转换为其潜在的概率图,作为组合优化技术适用性的说明。在所有可能的失效向量下测试了它们的最优性。
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