{"title":"A 14-bit DDS Circuit Design Based on CORDIC Algorithm","authors":"Yali Su, Zejie Kuang, Guohe Zhang, Li Sun","doi":"10.1109/ICIASE45644.2019.9074119","DOIUrl":null,"url":null,"abstract":"A hardware circuit design for high performance DDS(Direct Digital Synthesizer) is discussed here. With proper design of the phase amplitude conversion module, the output truncation error processing module, multi-bits DAC compatibility and phase accumulator, a 14-bit DDS circuit with SMIC 0.13um technology is presented based on CORDIC(Coordinate Rotation Digital Computer) algorithm. Compared with the lookup table method, higher speed performance can be achieved. The FPGA experiment results show that the circuit with operation frequency 200MHz consumes about 43320 equivalent gates and the frequency resolution reaches 0.0466 Hz. The circuit with 520MHz working frequency consumes about 64520 equivalent gates, while the frequency resolution is 0.121 Hz. And SFDR is about 112dB.","PeriodicalId":206741,"journal":{"name":"2019 IEEE International Conference of Intelligent Applied Systems on Engineering (ICIASE)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference of Intelligent Applied Systems on Engineering (ICIASE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIASE45644.2019.9074119","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A hardware circuit design for high performance DDS(Direct Digital Synthesizer) is discussed here. With proper design of the phase amplitude conversion module, the output truncation error processing module, multi-bits DAC compatibility and phase accumulator, a 14-bit DDS circuit with SMIC 0.13um technology is presented based on CORDIC(Coordinate Rotation Digital Computer) algorithm. Compared with the lookup table method, higher speed performance can be achieved. The FPGA experiment results show that the circuit with operation frequency 200MHz consumes about 43320 equivalent gates and the frequency resolution reaches 0.0466 Hz. The circuit with 520MHz working frequency consumes about 64520 equivalent gates, while the frequency resolution is 0.121 Hz. And SFDR is about 112dB.
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