B. Warren, W. Richardson, K. Kanegawa, C. Arnell, H. Shimizu, K. Nakai, S. Hara, K. Ichiba
{"title":"A one megabit SRAM fabricated with 1.2 mu technology","authors":"B. Warren, W. Richardson, K. Kanegawa, C. Arnell, H. Shimizu, K. Nakai, S. Hara, K. Ichiba","doi":"10.1109/WAFER.1989.47535","DOIUrl":null,"url":null,"abstract":"A monolithic 1-Mb static random-access memory (SRAM) with a typical access time of 55 ns, fabricated using 1.2- mu m CMOS technology, is described. The product incorporates a design approach that permits the manufacture of next-generation products (0.8- mu m 1-Mb SRAMs) on current, well-understood production processes. The yield history using this technique supports wafer-level repetitive structures such as memory, or processor/memory combinations. Supporting actual yield data are presented. The product is constructed of many small memories that are fabricated through metal 1, then tested and laser repaired and subsequently interconnected, using a nondiscretionary metal 2 layer, into a much larger memory system.<<ETX>>","PeriodicalId":412685,"journal":{"name":"[1989] Proceedings International Conference on Wafer Scale Integration","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1989] Proceedings International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WAFER.1989.47535","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
A monolithic 1-Mb static random-access memory (SRAM) with a typical access time of 55 ns, fabricated using 1.2- mu m CMOS technology, is described. The product incorporates a design approach that permits the manufacture of next-generation products (0.8- mu m 1-Mb SRAMs) on current, well-understood production processes. The yield history using this technique supports wafer-level repetitive structures such as memory, or processor/memory combinations. Supporting actual yield data are presented. The product is constructed of many small memories that are fabricated through metal 1, then tested and laser repaired and subsequently interconnected, using a nondiscretionary metal 2 layer, into a much larger memory system.<>
介绍了一种采用1.2 μ m CMOS技术制作的单片1mb静态随机存取存储器(SRAM),典型存取时间为55ns。该产品采用了一种设计方法,允许在当前的、众所周知的生产工艺上制造下一代产品(0.8 μ m 1mb sram)。使用该技术的良率历史支持晶圆级重复结构,如内存或处理器/内存组合。给出了支持实际产量的数据。该产品由许多小型存储器组成,这些存储器通过金属制造,然后测试和激光修复,随后使用非任意金属层连接成一个更大的存储系统。