Performance Evaluation of Mesh-based 3D NoCs

Abstract

The advances on 3D circuit integration have reignited the idea of processing-in-memory (PIM). In this paper, we evaluate 3D mesh-based NoC design for 3D-PIM systems. We study the stacked mesh (S-Mesh) which is a mesh-bus hybrid architecture for 3D NoCs that connects vertically stacked 2D meshes through buses. Previous S-Mesh studies have not addressed the problems and modifications needed at the building blocks of the network. We explain in details the internal structure of the S-Mesh, as well as, the problems and solutions of connecting 2D meshes using vertical buses. Also, we evaluate the performance of 3D NoC designs via two traffic patterns, one of which is a novel traffic pattern that better measures 3D-PIM systems performance. Our results show 15% performance improvement for the S-Mesh for zero-load packet latency while having a negligible decrease in saturation throughput.