Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process

Abstract

In this paper, standard cell design challenges for the 3nm process are introduced, solved, and optimized using the advanced MOL technology, AC P–N connection. In this methodology, each drain nodes of P and NMOS are connected using a single MOL layer (AC). Utilizing the AC P–N connection, standard cell library can be improved in three different ways. First, reduce the parasitic wire resistance by more than 20% and improve circuit reliability by alleviating a high current density. Second, Ceff improvement by composing only the MOL layer (AC) for the output node of the cell improves the standard cell speed up to 9.6%. Third, we propose a novel Flip-Flop (FF) structure optimized for AC P–N connection, thus improving the speed of the FF (1/TD2Q) by 9.1%.