Open-Source Fully-Synthesizable ADPLL for a Bluetooth Low-Energy Transmitter in 12nm FinFET Technology

Kyumin Kwon, Omar Abdelatty, D. Wentzloff
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引用次数: 3

Abstract

In this work, we present an open-source fully-synthesizable fractional-N ADPLL designed for a Bluetooth Low-Energy (BLE) transmitter (TX). A highly automated design flow is used to lower the barrier for new developers and to reduce porting cost. In the PLL, a novel two-step TDC (TSTDC) is proposed, which is amenable to P&R, and uses an embedded TDC (EMBTDC) and vernier delay-line TDC (DLTDC) as coarse and fine TDCs, respectively. This combination reduces the required DLTDC input time range by 5x and is used to measure and compensate the P&R induced non-linearity of the EMBTDC. The PLL is fabricated in 12-nm FinFET and demonstrated in a BLE-TX. BLE transmissions satisfy the standard requirements thanks to the reduced fractional spurs by abovementioned techniques. In a standalone PLL mode, the TSTDC reduced fractional spurs by 6.8 dB compared to an EMBTDC alone, and the proposed LUT-based calibration further reduced spurs by 7.5 dB in near-integer operation. The PLL supports frequency range of 1.8-2.7GHz and consumes 3.91mW at 2.4006 GHz, with a 40MHz reference, occupying area of 0.063mm2.
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12纳米FinFET技术的蓝牙低能量发射器的开源可完全合成ADPLL
在这项工作中,我们提出了一个开源的完全可合成的分数n ADPLL,专为蓝牙低功耗(BLE)发射机(TX)设计。高度自动化的设计流程用于降低新开发人员的门槛并降低移植成本。在锁相环中,提出了一种适用于P&R的新型两步TDC (TSTDC),并分别使用嵌入式TDC (EMBTDC)和游标延迟线TDC (DLTDC)作为粗TDC和细TDC。这种组合将所需的DLTDC输入时间范围减少了5倍,并用于测量和补偿EMBTDC的P&R引起的非线性。该锁相环采用12纳米FinFET制造,并在BLE-TX中进行了演示。由于采用上述技术减少了分式杂散,因此可以满足标准要求。在独立PLL模式下,与EMBTDC相比,TSTDC减少了6.8 dB的分数杂散,而基于lut的校准在近整数操作下进一步减少了7.5 dB的杂散。该锁相环支持1.8-2.7GHz频率范围,在2.4006 GHz时功耗为3.91mW,参考频率为40MHz,占用面积为0.063mm2。
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