{"title":"A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance","authors":"Guan-Ying Huang, Chun-Cheng Liu, Ying-Zu Lin, Soon-Jyh Chang","doi":"10.1109/ASSCC.2009.5357202","DOIUrl":null,"url":null,"abstract":"This paper reports a successive-approximation analog-to-digital converter (ADC) with low input capacitance. The 10-bit prototype is fabricated in a 0.13-µm CMOS process. Compared to conventional successive approximation ADCs, the proposed ADC reduces the input capacitance to 1.2 pF for 10-bit resolution. At 12 MS/s and 1.2-V supply, this ADC consumes 0.32 mW and achieves an SNDR of 50.89 dB, resulting in an FOM of 95 fJ/Conversion-step.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"14 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357202","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 26
Abstract
This paper reports a successive-approximation analog-to-digital converter (ADC) with low input capacitance. The 10-bit prototype is fabricated in a 0.13-µm CMOS process. Compared to conventional successive approximation ADCs, the proposed ADC reduces the input capacitance to 1.2 pF for 10-bit resolution. At 12 MS/s and 1.2-V supply, this ADC consumes 0.32 mW and achieves an SNDR of 50.89 dB, resulting in an FOM of 95 fJ/Conversion-step.
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