Chip assembly in the PLAYOUT VLSI design system

Abstract

Chip assembly in PLAYOUT is designed for top-down chip planning. An example of a three-level hierarchy demonstrates the new design strategy. Three-phase chip planning and chip assembly have close interaction to guarantee an exchange of constraints between levels of the hierarchy. Chip assembly is composed of two different functions: cell synthesis, and cell assembly. For cell synthesis, standard cell block layout is used to demonstrate a new strategy. Instead of generating the layouts of blocks in the same floorplan independently, layout proceeds in parallel and constraints like pin positions, shape and position of the blocks in the floorplan are exchanged dynamically. This method results in excellent adjustment of pin positions between cells and reduction of channel widths. Independent of the cell synthesis strategy is cell assembly, viewed as a topological compaction problem to refine the floorplans. A genetic algorithm is shown to solve this problem. Initial experimental results show the advantages of the new strategies.<>