Application of Design of Experiments (DOE) methods to high-speed interconnect validation

Abstract

A new method for validating interconnect performance has been demonstrated. The use of DOE permitted timely acquisition of data by optimizing the number of experiments (measurements) needed. The model fitting (RSM) of the data allowed for confident prediction across all high volume conditions, even though every case could not be tested. There were a number of new learnings and huge extensions to the ability to understand and characterize bus performance. One key learning was that buffer compensation works very well. Note that the edge rate at the receiver shows little variation across all measured conditions. In addition, the RSM models predict very little impact to setup/hold margins due to process and temperature. The RSM models also showed that motherboard length, motherboard impedance, and termination voltage have the most impact on FSB performance. This correlates very well with simulated interconnect results.