ROM-based finite state machines with PLA address modifiers

Proceedings EURO-DAC '92: European Design Automation Conference Pub Date : 1992-11-01 DOI:10.1109/EURDAC.1992.246232

T. Luba, K. Górski, L. Wronski

引用次数: 13

Abstract

An effective method for the synthesis of address modifiers in sequential circuits is described. The method, based on serial decomposition, substantially reduces the address modifier circuit complexity for a given microprogram memory size. It can be used effectively for PMS based designs and for full custom designs. The method was implemented in C++ on a PC. It was tested on standard finite state machine (FSM) benchmarks. Results indicate that for a wide range of cases the method gives a substantial (more than 50%) reduction of required ROM capacity, which may result in a saving of the silicon area in the actual full custom implementation.<>

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

带有PLA地址修饰符的基于rom的有限状态机

介绍了顺序电路中地址修饰符合成的一种有效方法。该方法基于串行分解，大大降低了给定微程序存储器大小的地址修改器电路的复杂度。它可以有效地用于基于PMS的设计和完全定制的设计。该方法在PC机上用c++实现。它在标准有限状态机(FSM)基准上进行了测试。结果表明，在广泛的情况下，该方法提供了大量(超过50%)减少所需的ROM容量，这可能导致在实际的完全定制实现中节省硅面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

Proceedings EURO-DAC '92: European Design Automation Conference

自引率

0.00%

发文量

期刊最新文献

New design error modeling and metrics for design validation Embedded pin assignment for top down system design An exact analytic technique for simulating uniform RC lines Towards a standard VHDL synthesis package Generating pipelined datapaths using reduction techniques to shorten critical paths