Modeling, simulation and layout synthesis for giga scale CMOS VLSI

Abstract

Summary form only given, as follows. With continuing proliferation of CMOS technology, we are approaching the era of giga-scale VLSI integration with lower power requirement. It would not be surprising to any member of the VLSI community that the validity of many CAD models become obsolete in the deep submicron technology. Also, the required chip complexity increases faster than what designers can afford in even shorter design cycle time. In order to manage the design complexity and contain the increase in the design effort of VLSI chips, it is critically important to fully automate the layout of VLSI circuits in a manner the finished layout meets all the design objectives such as timing, area, reliability constraints with high yield. Here the author considers new MOS models for deep submicron technologies, fast and accurate simulation techniques for VLSI circuits, MOS reliability modeling and diagnosis, and timing-driven layout CMOS synthesis techniques. FPGA, standard cells based design and full custom design cases are considered. For FPGA, timing-driven partitioning is considered along with new CAD tool development trends. For standard cells based design, gate sizing techniques for meeting timing and low-power constraints with minimum area are discussed. For full custom design, an integrated environment for compact layout platforms, triple metal routing techniques and transistor sizing algorithms is discussed.