Design of Low Area and Low Power Systolic Serial Parallel Multiplier using CNTFETs

Abstract

In this paper, we designed a CNTFET based Systolic serial parallel multiplier. This systolic serial parallel multiplier is 100% efficient and operates on selection of either 0, X, 2X, 3X product terms, where X is a serial input to the multiplier. This multiplier design requires modules like 4$\times$ 1 MUX, 2$\times$ 1 MUX, OR gate, Full Adder, and Delay elements known as D-Flipflops. In this paper, we have used Gate Diffusion Input (GDI) technique for designing combinational logic gates to reduce the area and power. This multiplier design require more number of D-Flipflops compared to other logic circuits. In this paper we proposed a new D-Flipflop with 10 transistors with a single clock load and a IOT-based full adder design to reduce area and power consumption. The proposed systolic serial parallel multiplier has a saving of 41% of area compared to recent design. Our simulation results shows that proposed systolic serial parallel multiplier design has a reduction in transistor count by 82.65%, a drop in power dissipation by 95.96%, decrease in delay by 98.12% and a decrease in PDP by 99.92% compared to the existing systolic array multiplier.