A2CM2: aging-aware cache memory management technique

Abstract

Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect which is leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most prone modules to NBTI. Variations in duty cycle and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and distributes uniformly stress condition for each line. The simulation results show that the proposed technique reduces the NBTI effect in I-cache significantly as compared to normal operation. Moreover, the energy consumption and the performance overheads of the proposed technique are negligible.