Behavioral fault simulation in VHDL

Abstract

Two tools which facilitate a fault simulation of behavioral models described using the VHSIC hardware description language (VHDL) are presented. The first tool is the behavioral fault mapper (BFM). The BFM algorithm accepts a fault-free VHDL model and a fault-list of N faults from which it produces N faulty models. The process of mapping the faults in the fault-list onto copies of the original VHDL model is automated. The N faulty models are immediately suitable for fault simulation. The second tool presented is test bench generator (TBG). The TBG algorithm creates the VHDL testbench and all other files necessary to complete a batch-mode fault simulation of the N faulty models.<>