16.2 A 9GS/s 1GHz-BW oversampled continuous-time pipeline ADC achieving −161dBFS/Hz NSD

Abstract

In traditional ADCs the input signal is sampled at the front-end by a switched-capacitor circuit and all internal signals are processed in discrete-time (DT) even though the front-end sampler introduces artifacts such as aliasing, noise folding, and high-peak ADC driving current to charge the input sampling capacitor. In ΔΣ ADCs, those issues are resolved by replacing the DT loop filter with a continuous-time (CT) implementation which relaxes the pre-filter and driver requirements in the signal chain thus reducing the overall signal chain power consumption. CTΔΣs also introduce additional benefits such as 2–3× higher clocking capability in the same process node and low-power internal opamps due to relaxed noise, loading, and gain bandwidth requirements. Since these CT benefits are not exclusive to the ΔΣ architecture, other ADC architectures could similarly benefit by replacing DT blocks with CT ones. This paper presents a CT pipeline ADC, which processes the input and residue signals with CT circuitry throughout all the pipeline stages. The combination of CT signal processing with the pipeline architecture realizes an ADC system inheriting the CT benefits while achieving a digitization bandwidth (BW) more than 2× greater than that of CT ΔΣ ADCs, which is comparable to DT pipeline ADCs in the same process node.