Pub Date : 2017-03-02DOI: 10.1109/ISSCC.2017.7870294
B. Sadhu, Y. Tousi, J. Hallin, Stefan Sahl, S. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, N. Mazor, B. Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, E. Westesson, Jan-Erik Thillberg, L. Rexberg, M. Yeck, X. Gu, D. Friedman, A. Valdes-Garcia
Next-generation mobile technology (5G) aims to provide an improved experience through higher data-rates, lower latency, and improved link robustness. Millimeter-wave phased arrays offer a path to support multiple users at high data-rates using high-bandwidth directional links between the base station and mobile devices. To realize this vision, a phased-array-based pico-cell must support a large number of precisely controlled beams, yet be compact and power efficient. These system goals have significant mm-wave radio interface implications, including scalability of the RFIC+antenna-array solution, increase in the number of concurrent beams by supporting dual polarization, precise beam steering, and high output power without sacrificing TX power efficiency. Packaged Si-based phased arrays [1–3] with nonconcurrent dual-polarized TX and RX operation [2,3], concurrent dual-polarized RX operation [3] and multi-IC scaling [3,4] have been demonstrated. However, support for concurrent dual-polarized operation in both RX and TX remains unaddressed, and high output power comes at the cost of power consumption, cooling complexity and increased size. The RFIC reported here addresses these challenges. It supports concurrent and independent dual-polarized operation in TX and RX modes, and is compatible with a volume-efficient, scaled, antenna-in-package array. A new TX/RX switch at the shared antenna interface enables high output power without sacrificing TX efficiency, and a t-line-based phase shifter achieves <1° RMS error and <5° phase steps for precise beam control.
{"title":"7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication","authors":"B. Sadhu, Y. Tousi, J. Hallin, Stefan Sahl, S. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, N. Mazor, B. Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, E. Westesson, Jan-Erik Thillberg, L. Rexberg, M. Yeck, X. Gu, D. Friedman, A. Valdes-Garcia","doi":"10.1109/ISSCC.2017.7870294","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870294","url":null,"abstract":"Next-generation mobile technology (5G) aims to provide an improved experience through higher data-rates, lower latency, and improved link robustness. Millimeter-wave phased arrays offer a path to support multiple users at high data-rates using high-bandwidth directional links between the base station and mobile devices. To realize this vision, a phased-array-based pico-cell must support a large number of precisely controlled beams, yet be compact and power efficient. These system goals have significant mm-wave radio interface implications, including scalability of the RFIC+antenna-array solution, increase in the number of concurrent beams by supporting dual polarization, precise beam steering, and high output power without sacrificing TX power efficiency. Packaged Si-based phased arrays [1–3] with nonconcurrent dual-polarized TX and RX operation [2,3], concurrent dual-polarized RX operation [3] and multi-IC scaling [3,4] have been demonstrated. However, support for concurrent dual-polarized operation in both RX and TX remains unaddressed, and high output power comes at the cost of power consumption, cooling complexity and increased size. The RFIC reported here addresses these challenges. It supports concurrent and independent dual-polarized operation in TX and RX modes, and is compatible with a volume-efficient, scaled, antenna-in-package array. A new TX/RX switch at the shared antenna interface enables high output power without sacrificing TX efficiency, and a t-line-based phase shifter achieves <1° RMS error and <5° phase steps for precise beam control.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127449179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-02DOI: 10.1109/ISSCC.2017.7870347
R. Bhat, Jin Zhou, H. Krishnaswamy
Digital power amplifiers and transmitters have drawn significant interest in the recent past due to their reconfigurability, compatibility with CMOS technology scaling and DSP, and potential for automated design synthesis [1–5]. While significant progress has been made in achieving moderate output power levels in CMOS, wideband modulation, and high efficiency under back-off, out-of-band emissions remain an unsolved problem. The elimination of the analog reconstruction filter that follows the DAC in a conventional analog transmitter implies that broadband DAC quantization noise appears at the output of the transmitter unfiltered. Quantization noise can be suppressed by increasing resolution and/or sampling rate, but to meet the challenging −150 to −160dBc/Hz out-of-band (OOB and specifically RX-band) noise requirement of FDD with conventional duplexers, nearly 12b at 0.5GS/s is required. Such a high effective number of bits (ENOB) is extremely challenging in digital PAs given their strong output nonlinearity. Consequently, while low-power modulators are able to approach −150dBc/Hz RX-band noise floor and below [6], state-of-the-art digital transmitters achieve −130 to −135dBc/Hz RX-band noise, nearly 20dB or 100× away [2–4]. Embedding mixed-domain FIR filtering into digital transmitters to create notches in the RX band has been proposed [4,7], but, while successful in low-power modulators [7], nonlinearity significantly limits notch depth to <10dB in digital PAs [4]. Further, notch bandwidth (BW) is far less than 20MHz, the typical LTE BW, in the simple two-tap FIR structures that have been explored [4].
{"title":"13.10 A >1W 2.2GHz switched-capacitor digital power amplifier with wideband mixed-domain multi-tap FIR filtering of OOB noise floor","authors":"R. Bhat, Jin Zhou, H. Krishnaswamy","doi":"10.1109/ISSCC.2017.7870347","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870347","url":null,"abstract":"Digital power amplifiers and transmitters have drawn significant interest in the recent past due to their reconfigurability, compatibility with CMOS technology scaling and DSP, and potential for automated design synthesis [1–5]. While significant progress has been made in achieving moderate output power levels in CMOS, wideband modulation, and high efficiency under back-off, out-of-band emissions remain an unsolved problem. The elimination of the analog reconstruction filter that follows the DAC in a conventional analog transmitter implies that broadband DAC quantization noise appears at the output of the transmitter unfiltered. Quantization noise can be suppressed by increasing resolution and/or sampling rate, but to meet the challenging −150 to −160dBc/Hz out-of-band (OOB and specifically RX-band) noise requirement of FDD with conventional duplexers, nearly 12b at 0.5GS/s is required. Such a high effective number of bits (ENOB) is extremely challenging in digital PAs given their strong output nonlinearity. Consequently, while low-power modulators are able to approach −150dBc/Hz RX-band noise floor and below [6], state-of-the-art digital transmitters achieve −130 to −135dBc/Hz RX-band noise, nearly 20dB or 100× away [2–4]. Embedding mixed-domain FIR filtering into digital transmitters to create notches in the RX band has been proposed [4,7], but, while successful in low-power modulators [7], nonlinearity significantly limits notch depth to <10dB in digital PAs [4]. Further, notch bandwidth (BW) is far less than 20MHz, the typical LTE BW, in the simple two-tap FIR structures that have been explored [4].","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127455945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-02DOI: 10.1109/ISSCC.2017.7870342
M. Kosunen, Jerry Lemberg, Mikko Martelius, Enrico Roverato, Tero Nieminen, Mikko Englund, K. Stadius, L. Anttila, J. Pallonen, Mikko Valkama, J. Ryynänen
Advanced wireless radio standards set stringent requirements on the bandwidth, frequency range and reconfigurability of base-station transmitters. Recently, the outphasing concept has shown promise of wide bandwidth while taking advantage of process scaling with extensive exploitation of rail-to-rail signaling. Recent outphasing transmitter designs have often focused on power-amplifier (PA) and power-combiner implementations while omitting the phase modulator [1,2]. Moreover, previously reported transmitters with integrated digital phase modulators have only shown bandwidths up to 40MHz [3,4], although 133MHz has been demonstrated at 10GHz carrier frequency utilizing phase modulators based on conventional IQ-DACs [5]. Thus, digital-intensive outphasing transmitters capable of modulation with hundreds of MHz bandwidth at existing cellular frequency bands have not yet been published. To address the aforementioned challenge, this paper introduces a multilevel outphasing transmitter with four amplitude levels, including the first prototype implementation based on the digital interpolating phase modulator concept [6]. The transmitter is targeted for 5G picocell base stations and has been verified to operate with instantaneous bandwidth up to 400MHz. In addition, the developed phase modulator eliminates the need for complex on-chip frequency synthesizers by introducing digital carrier frequency generation, demonstrated between 0.35 and 2.6GHz, while utilizing a single 1.8GHz reference clock.
{"title":"13.5 A 0.35-to-2.6GHz multilevel outphasing transmitter with a digital interpolating phase modulator enabling up to 400MHz instantaneous bandwidth","authors":"M. Kosunen, Jerry Lemberg, Mikko Martelius, Enrico Roverato, Tero Nieminen, Mikko Englund, K. Stadius, L. Anttila, J. Pallonen, Mikko Valkama, J. Ryynänen","doi":"10.1109/ISSCC.2017.7870342","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870342","url":null,"abstract":"Advanced wireless radio standards set stringent requirements on the bandwidth, frequency range and reconfigurability of base-station transmitters. Recently, the outphasing concept has shown promise of wide bandwidth while taking advantage of process scaling with extensive exploitation of rail-to-rail signaling. Recent outphasing transmitter designs have often focused on power-amplifier (PA) and power-combiner implementations while omitting the phase modulator [1,2]. Moreover, previously reported transmitters with integrated digital phase modulators have only shown bandwidths up to 40MHz [3,4], although 133MHz has been demonstrated at 10GHz carrier frequency utilizing phase modulators based on conventional IQ-DACs [5]. Thus, digital-intensive outphasing transmitters capable of modulation with hundreds of MHz bandwidth at existing cellular frequency bands have not yet been published. To address the aforementioned challenge, this paper introduces a multilevel outphasing transmitter with four amplitude levels, including the first prototype implementation based on the digital interpolating phase modulator concept [6]. The transmitter is targeted for 5G picocell base stations and has been verified to operate with instantaneous bandwidth up to 400MHz. In addition, the developed phase modulator eliminates the need for complex on-chip frequency synthesizers by introducing digital carrier frequency generation, demonstrated between 0.35 and 2.6GHz, while utilizing a single 1.8GHz reference clock.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122458701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-02DOI: 10.1109/ISSCC.2017.7870360
Carmine Garripoli, J. Steen, E. Smits, G. Gelinck, A. Roermund, E. Cantatore
Amorphous IGZO (a-IGZO) TFTs fabricated on flexible large-area substrates provide better mobility than a-Si or organic counterparts and good uniformity. These features make a-IGZO TFTs an attractive technology for large-area sensing (e.g. strain, pressure, IR), low-cost RFIDs augmented with sensors and monitoring of biopotentials. In this context, it is crucial to accurately transform analogue sensor signals in a robust representation. The most common choice is a synchronous digital word, but a two-level PWM representation is another interesting possibility. Binary PWM can be transmitted on wire or via RF amplitude modulation with high immunity to noise and interferers.
{"title":"15.3 An a-IGZO asynchronous delta-sigma modulator on foil achieving up to 43dB SNR and 40dB SNDR in 300Hz bandwidth","authors":"Carmine Garripoli, J. Steen, E. Smits, G. Gelinck, A. Roermund, E. Cantatore","doi":"10.1109/ISSCC.2017.7870360","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870360","url":null,"abstract":"Amorphous IGZO (a-IGZO) TFTs fabricated on flexible large-area substrates provide better mobility than a-Si or organic counterparts and good uniformity. These features make a-IGZO TFTs an attractive technology for large-area sensing (e.g. strain, pressure, IR), low-cost RFIDs augmented with sensors and monitoring of biopotentials. In this context, it is crucial to accurately transform analogue sensor signals in a robust representation. The most common choice is a synchronous digital word, but a two-level PWM representation is another interesting possibility. Binary PWM can be transmitted on wire or via RF amplitude modulation with high immunity to noise and interferers.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124546659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-02DOI: 10.1109/ISSCC.2017.7870329
Qing Dong, Yejoong Kim, Inhee Lee, M. Choi, Ziyun Li, Jingcheng Wang, Kaiyuan Yang, Yen-Po Chen, J. Dong, Minchang Cho, Gyouho Kim, W. Chang, Yun-Sheng Chen, Y. Chih, D. Blaauw, D. Sylvester
Miniature sensor nodes are ideal for monitoring environmental conditions in emerging applications such as oil exploration. One key requirement for sensor nodes is embedded non-volatile memory for compact and retentive data storage in the event that the sensor power source is exhausted. Non-volatile memory also allows for near-zero standby power modes, which are particularly challenging to achieve at high temperatures when using SRAM in standby due to the exponential rise in leakage with temperature, which rapidly degrades battery life (Fig. 11.2.1). However, traditional NOR flash requires mW-level program and erase power, which cannot be sustained by mm-scale batteries with internal resistances >10kΩ To address this issue, we propose an ultra-low power NOR flash design and demonstrate its integration into a complete sensor system that is specifically designed for environmental monitoring under high temperature conditions: such as when injected into geothermal or oil wells.
{"title":"11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes","authors":"Qing Dong, Yejoong Kim, Inhee Lee, M. Choi, Ziyun Li, Jingcheng Wang, Kaiyuan Yang, Yen-Po Chen, J. Dong, Minchang Cho, Gyouho Kim, W. Chang, Yun-Sheng Chen, Y. Chih, D. Blaauw, D. Sylvester","doi":"10.1109/ISSCC.2017.7870329","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870329","url":null,"abstract":"Miniature sensor nodes are ideal for monitoring environmental conditions in emerging applications such as oil exploration. One key requirement for sensor nodes is embedded non-volatile memory for compact and retentive data storage in the event that the sensor power source is exhausted. Non-volatile memory also allows for near-zero standby power modes, which are particularly challenging to achieve at high temperatures when using SRAM in standby due to the exponential rise in leakage with temperature, which rapidly degrades battery life (Fig. 11.2.1). However, traditional NOR flash requires mW-level program and erase power, which cannot be sustained by mm-scale batteries with internal resistances >10kΩ To address this issue, we propose an ultra-low power NOR flash design and demonstrate its integration into a complete sensor system that is specifically designed for environmental monitoring under high temperature conditions: such as when injected into geothermal or oil wells.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130771179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-02DOI: 10.1109/ISSCC.2017.7870404
Hsi-Shou Wu, Zhengya Zhang, M. Papaefthymiou
This paper presents an ANSI S1.11 1/3-octave filter-bank chip for binaural hearing aids with two microphones per ear. Binaural multimicrophone systems significantly suppress noise interference and preserve interaural time cues at the cost of significantly higher computational and power requirements than monophonic single-microphone systems. With clock rates around the 1MHz mark, these systems are ideal candidates for low-power implementation through charge-recovery design. At such low clock frequencies, however, charge-recovery logic suffers from short-circuit currents that limit its theoretical energy efficiency [1]. The chip described in this paper is designed in 65nm CMOS using a new charge-recovery logic, called zero-short-circuit-current (ZSCC) logic, that drastically reduces short-circuit current. It processes 4 input streams at 1.75MHz with a charge recovery rate of 92%, achieving 9.7× lower power per input compared with the 40nm monophonic single-input chip that represents the published state of the art [2].
{"title":"20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS","authors":"Hsi-Shou Wu, Zhengya Zhang, M. Papaefthymiou","doi":"10.1109/ISSCC.2017.7870404","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870404","url":null,"abstract":"This paper presents an ANSI S1.11 1/3-octave filter-bank chip for binaural hearing aids with two microphones per ear. Binaural multimicrophone systems significantly suppress noise interference and preserve interaural time cues at the cost of significantly higher computational and power requirements than monophonic single-microphone systems. With clock rates around the 1MHz mark, these systems are ideal candidates for low-power implementation through charge-recovery design. At such low clock frequencies, however, charge-recovery logic suffers from short-circuit currents that limit its theoretical energy efficiency [1]. The chip described in this paper is designed in 65nm CMOS using a new charge-recovery logic, called zero-short-circuit-current (ZSCC) logic, that drastically reduces short-circuit current. It processes 4 input streams at 1.75MHz with a charge recovery rate of 92%, achieving 9.7× lower power per input compared with the 40nm monophonic single-input chip that represents the published state of the art [2].","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114213616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-02DOI: 10.1109/ISSCC.2017.7870321
Wen-Chuen Liu, Pourya Assem, Y. Lei, P. Hanumolu, R. Pilawa-Podgurski
Owing to the need for low power consumption, portable and wearable electronics operate at low voltages, typically below 1V, with recent designs in near- and subthreshold operation resulting in voltages down to 0.3 to 0.5V. Meanwhile, voltage range of the most common energy source - the Li-ion battery - is 3 to 4.2V, motivating the need for compact power converters capable of large conversion ratio with wide and efficient voltage regulation.
{"title":"10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS","authors":"Wen-Chuen Liu, Pourya Assem, Y. Lei, P. Hanumolu, R. Pilawa-Podgurski","doi":"10.1109/ISSCC.2017.7870321","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870321","url":null,"abstract":"Owing to the need for low power consumption, portable and wearable electronics operate at low voltages, typically below 1V, with recent designs in near- and subthreshold operation resulting in voltages down to 0.3 to 0.5V. Meanwhile, voltage range of the most common energy source - the Li-ion battery - is 3 to 4.2V, motivating the need for compact power converters capable of large conversion ratio with wide and efficient voltage regulation.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124474457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-02DOI: 10.1109/ISSCC.2017.7870364
B. Nasri, Ting Wu, A. Alharbi, Mayank Gupta, RamKumar RanjithKumar, Sunit P. Sebastian, Yue Wang, R. Kiani, D. Shahrjerdi
Understanding dopamine (DA) signaling in the brain is essential for advancing our knowledge of pathological disorders such as drug addiction, Parkinson's disease, and schizophrenia. Currently, fast-scan cyclic voltammetry (FSCV) with carbon microfiber (CMF) electrodes is the method of choice in neuroscience labs for monitoring the concentration of phasic (transient) DA release. This method offers sub-second temporal resolution and high specificity because the signal of interest occurs at a known potential. However, existing CMF electrodes are bulky, limiting the spatial resolution to single-site measurements. Further, they are produced through manual processes (e.g. cutting CMFs under optical microscope), thus introducing significant device variability [1]. Lastly, when long probes (3-to-5cm) are used to monitor DA release in deep brain structures of large animals, environmental noise severely diminishes the detection limit [1]. To address these problems, we combine advances in nanofabrication with silicon chip manufacturing to create a heterogeneous integrated CMOS-graphene sensor for accurate measurement of DA with high spatiotemporal resolution (Fig. 15.7.1).
{"title":"15.7 Heterogeneous integrated CMOS-graphene sensor array for dopamine detection","authors":"B. Nasri, Ting Wu, A. Alharbi, Mayank Gupta, RamKumar RanjithKumar, Sunit P. Sebastian, Yue Wang, R. Kiani, D. Shahrjerdi","doi":"10.1109/ISSCC.2017.7870364","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870364","url":null,"abstract":"Understanding dopamine (DA) signaling in the brain is essential for advancing our knowledge of pathological disorders such as drug addiction, Parkinson's disease, and schizophrenia. Currently, fast-scan cyclic voltammetry (FSCV) with carbon microfiber (CMF) electrodes is the method of choice in neuroscience labs for monitoring the concentration of phasic (transient) DA release. This method offers sub-second temporal resolution and high specificity because the signal of interest occurs at a known potential. However, existing CMF electrodes are bulky, limiting the spatial resolution to single-site measurements. Further, they are produced through manual processes (e.g. cutting CMFs under optical microscope), thus introducing significant device variability [1]. Lastly, when long probes (3-to-5cm) are used to monitor DA release in deep brain structures of large animals, environmental noise severely diminishes the detection limit [1]. To address these problems, we combine advances in nanofabrication with silicon chip manufacturing to create a heterogeneous integrated CMOS-graphene sensor for accurate measurement of DA with high spatiotemporal resolution (Fig. 15.7.1).","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130114816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-02DOI: 10.1109/ISSCC.2017.7870296
Li-Xuan Chuo, Yao Shi, Zhihong Luo, N. Chiotellis, Z. Foo, Gyouho Kim, Yejoong Kim, A. Grbic, D. Wentzloff, Hun-Seok Kim, D. Blaauw
Enabling long range (>10m) wireless communication in non-line-of sight (NLOS) scenarios would dramatically expand the application space and usability of mm-scale wireless sensor nodes. The major technical challenges posed by a mm-scale form-factor are poor antenna efficiency and the small instantaneous current limit (∼10s of μA) of thin-film batteries. We address these challenges in several ways: 1) We found that a magnetic dipole antenna achieves better efficiency at an electrically-small size than an electric dipole, when the antennas are resonated with off-chip lumped components. In addition, the high impedance of electrically-small electric dipoles (∼4kΩ compared to 10Ω for the magnetic antenna) requires an impractically large off-chip inductor to resonate. 2) By simultaneously considering the magnetic dipole efficiency, frequency-dependent path-loss, and wall penetration loss, we found that a 915MHz carrier frequency is optimal for a 3×3×3mm3 sensor node in NLOS asymmetric communication with a gateway. This is despite the resulting low antenna efficiency (0.21%) which typically drives mm-scale radios to operate at ≫1GHz frequency [1]. 3) In transmit (TX) mode, instead of using a PA and PLL, we utilize a cross-coupled driver to resonate the magnetic antenna at 915MHz with a quality factor (Q) of 110 in order to reduce overall power consumption. 4) In receive (RX) mode, we propose an approach of reusing the cross-coupled driver in a non-oscillating mode to raise the Q of the resonant tank to 300, resulting in 49dB voltage gain at 43µW, thereby replacing a power-hungry LNA and bulky off-chip filter. 5) A sparse pulse-position modulation (PPM) combined with a sensor-initiation communication protocol [2] shifts the power-hungry calibration of frequency offset to the gateway, enabling crystal-free radio design. The complete radio, including the transceiver IC, a 3D antenna, off-chip capacitors, a processor, a power management unit (PMU) and memory, is integrated within a 3×3×3mm3 sensor node, demonstrating stand-alone bi-directional 20m NLOS wireless communication with variable data rates of 30b/s to 30.3kb/s for TX and 7.8kb/s to 62.5kb/s for RX. The transmitter generates −26.9 dBm equivalent isotropically radiated power (EIRP) consuming 2mW power and the receiver has a sensitivity of −93dBm consuming 1.85mW.
{"title":"7.4 A 915MHz asymmetric radio using Q-enhanced amplifier for a fully integrated 3×3×3mm3 wireless sensor node with 20m non-line-of-sight communication","authors":"Li-Xuan Chuo, Yao Shi, Zhihong Luo, N. Chiotellis, Z. Foo, Gyouho Kim, Yejoong Kim, A. Grbic, D. Wentzloff, Hun-Seok Kim, D. Blaauw","doi":"10.1109/ISSCC.2017.7870296","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870296","url":null,"abstract":"Enabling long range (>10m) wireless communication in non-line-of sight (NLOS) scenarios would dramatically expand the application space and usability of mm-scale wireless sensor nodes. The major technical challenges posed by a mm-scale form-factor are poor antenna efficiency and the small instantaneous current limit (∼10s of μA) of thin-film batteries. We address these challenges in several ways: 1) We found that a magnetic dipole antenna achieves better efficiency at an electrically-small size than an electric dipole, when the antennas are resonated with off-chip lumped components. In addition, the high impedance of electrically-small electric dipoles (∼4kΩ compared to 10Ω for the magnetic antenna) requires an impractically large off-chip inductor to resonate. 2) By simultaneously considering the magnetic dipole efficiency, frequency-dependent path-loss, and wall penetration loss, we found that a 915MHz carrier frequency is optimal for a 3×3×3mm3 sensor node in NLOS asymmetric communication with a gateway. This is despite the resulting low antenna efficiency (0.21%) which typically drives mm-scale radios to operate at ≫1GHz frequency [1]. 3) In transmit (TX) mode, instead of using a PA and PLL, we utilize a cross-coupled driver to resonate the magnetic antenna at 915MHz with a quality factor (Q) of 110 in order to reduce overall power consumption. 4) In receive (RX) mode, we propose an approach of reusing the cross-coupled driver in a non-oscillating mode to raise the Q of the resonant tank to 300, resulting in 49dB voltage gain at 43µW, thereby replacing a power-hungry LNA and bulky off-chip filter. 5) A sparse pulse-position modulation (PPM) combined with a sensor-initiation communication protocol [2] shifts the power-hungry calibration of frequency offset to the gateway, enabling crystal-free radio design. The complete radio, including the transceiver IC, a 3D antenna, off-chip capacitors, a processor, a power management unit (PMU) and memory, is integrated within a 3×3×3mm3 sensor node, demonstrating stand-alone bi-directional 20m NLOS wireless communication with variable data rates of 30b/s to 30.3kb/s for TX and 7.8kb/s to 62.5kb/s for RX. The transmitter generates −26.9 dBm equivalent isotropically radiated power (EIRP) consuming 2mW power and the receiver has a sensitivity of −93dBm consuming 1.85mW.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122170761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-02DOI: 10.1109/ISSCC.2017.7870476
R. Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, A. Elmallah, P. Hanumolu
Serial link transceivers that can operate across a wide range of data rates offer flexibility and rapid realization of single-chip multi-standard solutions. The ability to independently control the data rate of each lane in a multi-lane transceiver with fine granularity is also valuable [1,2]. The implementation of such transceivers would require analog front-ends and clocking circuits that can operate over a wide range of frequencies. As a result, compared to transceivers that are optimized to operate at one single data rate, flexible-rate transceivers are power and area hungry [1]. Because a single PLL cannot generate clocks across the entire interface operating range, [1,2] use multiple LC tanks, carefully optimized waveform shaping circuits, power hungry clock distribution, and complex frequency planning methods.
{"title":"29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS","authors":"R. Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, A. Elmallah, P. Hanumolu","doi":"10.1109/ISSCC.2017.7870476","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870476","url":null,"abstract":"Serial link transceivers that can operate across a wide range of data rates offer flexibility and rapid realization of single-chip multi-standard solutions. The ability to independently control the data rate of each lane in a multi-lane transceiver with fine granularity is also valuable [1,2]. The implementation of such transceivers would require analog front-ends and clocking circuits that can operate over a wide range of frequencies. As a result, compared to transceivers that are optimized to operate at one single data rate, flexible-rate transceivers are power and area hungry [1]. Because a single PLL cannot generate clocks across the entire interface operating range, [1,2] use multiple LC tanks, carefully optimized waveform shaping circuits, power hungry clock distribution, and complex frequency planning methods.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133437417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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