A low power zero-crossing pipeline-SAR ADC with on-chip dynamically loaded pre-charged reference

Abstract

A dynamically loaded pre-charged reference technique for low power zero-crossing pipeline-SAR ADCs is presented. Power hungry reference buffers are eliminated and the loading from the reference capacitors is also reduced, thus improving the ADC noise performance. The 65-nm CMOS ADC prototype has an SFDR/SNR/SNDR of 77dB/70dB/66dB at 25MHz, while consuming 4.8mW at 50MS/s, including all the power for the reference generation and distribution.