Soft-errors resilient logic optimization for low power

Abstract

This paper is about a single event upset resilient logic design optimization technique for sub-100nm technology nodes. The proposed technique can be used for both combinational as well as sequential circuits. In order to make a logic circuit robust for a transient error, the well known gate sizing technique is used. A 65nm inverters based master slave flip flop is considered for the case study. The result shows a trade off between the robustness and the performance (power consumption and operational speed) while performing design optimization for a single event upset. Furthermore, it shows that the width of devices cannot be increased arbitrarily in order to make a flip flop resilient since it can result in timing violation. The proposed design optimization technique incorporates the timing aspects and finds the optimal widths that make a gate robust against a single event upset.