Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313867
Liang Chen, M. Tahoori
Soft error is becoming one of the major reliability concerns with continuously shrinking transistor size. Low level transient events may result in multiple correlated bit flips at high level. Considering this correlation effect is essential for accurate error rate estimation and efficient error mitigation. This paper proposes a novel framework to address this correlation issue at logic level. Based on the concept of error propagation function, graph transformation techniques are utilized to convert the error probability and correlation problem into the computation of signal probability and correlation. The experimental results show that compared with Monte-Carlo simulation, our approach is 72× faster, while the average inaccuracy of error probability estimation is below 0.006.
{"title":"An efficient probability framework for error propagation and correlation estimation","authors":"Liang Chen, M. Tahoori","doi":"10.1109/IOLTS.2012.6313867","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313867","url":null,"abstract":"Soft error is becoming one of the major reliability concerns with continuously shrinking transistor size. Low level transient events may result in multiple correlated bit flips at high level. Considering this correlation effect is essential for accurate error rate estimation and efficient error mitigation. This paper proposes a novel framework to address this correlation issue at logic level. Based on the concept of error propagation function, graph transformation techniques are utilized to convert the error probability and correlation problem into the computation of signal probability and correlation. The experimental results show that compared with Monte-Carlo simulation, our approach is 72× faster, while the average inaccuracy of error probability estimation is below 0.006.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125809874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313836
C. Bernardeschi, Luca Cassano, A. Domenici
We propose an un-excitability prover for Single Event Upset (SEU) faults affecting the configuration memory of logic resources of SRAM-FPGA systems. In particular, we focus on the subset of untestable faults that cannot even be excited, with the aim of optimizing the generation of test patterns, in particular for in-service testing. SEUs in configuration bits of the logic resources actually used by the system are addressed. This makes our fault model much more accurate than the classical stuck-at fault model. The tool relies on the SAL specification language for the modeling of netlists, and on the SAL model checker for the proof of the un-excitability of faults. Results from the application of the tool to some circuits from the ISCAS and ITC benchmarks are reported.
{"title":"SEU-X: A SEu un-excitability prover for SRAM-FPGAs","authors":"C. Bernardeschi, Luca Cassano, A. Domenici","doi":"10.1109/IOLTS.2012.6313836","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313836","url":null,"abstract":"We propose an un-excitability prover for Single Event Upset (SEU) faults affecting the configuration memory of logic resources of SRAM-FPGA systems. In particular, we focus on the subset of untestable faults that cannot even be excited, with the aim of optimizing the generation of test patterns, in particular for in-service testing. SEUs in configuration bits of the logic resources actually used by the system are addressed. This makes our fault model much more accurate than the classical stuck-at fault model. The tool relies on the SAL specification language for the modeling of netlists, and on the SAL model checker for the proof of the un-excitability of faults. Results from the application of the tool to some circuits from the ISCAS and ITC benchmarks are reported.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125437553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313857
A. Burg, O. Keren
The paper presents an embedded self test circuit for adaptive systems whose exact specification is unknown. In particular, a functional testing mechanism for systems that have an acceptable representation as polynomials of low order is introduced. The testing mechanism is based on linear-checks and is suitable for Walsh transform based architectures. The paper shows that it is possible to define a small set of linear-checks which does not depend on the actual functionality that the hardware has converged to. Moreover, the check-set can be defined even without knowing the number of input variables nor their precision. In addition, the implementation cost of this testing scheme is negligible in respect to the cost of overall system.
{"title":"Functional level embedded self testing for Walsh transform based adaptive hardware","authors":"A. Burg, O. Keren","doi":"10.1109/IOLTS.2012.6313857","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313857","url":null,"abstract":"The paper presents an embedded self test circuit for adaptive systems whose exact specification is unknown. In particular, a functional testing mechanism for systems that have an acceptable representation as polynomials of low order is introduced. The testing mechanism is based on linear-checks and is suitable for Walsh transform based architectures. The paper shows that it is possible to define a small set of linear-checks which does not depend on the actual functionality that the hardware has converged to. Moreover, the check-set can be defined even without knowing the number of input variables nor their precision. In addition, the implementation cost of this testing scheme is negligible in respect to the cost of overall system.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132011871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313864
A. Chaudhari, J. Abraham
Hardware based execution monitoring of applications holds the promise for an effective and tamper-proof solution for intrusion detection on processor. This paper presents a practical hardware based intrusion detection framework which uses stream cipher based hashing techniques for runtime control flow and instruction integrity monitoring. This framework enables accurate monitoring of the control flow of a process with an instruction level granularity. Additional hardware required for implementation of our framework has very low power and area overheads which makes it possible to practically implement execution monitoring even on embedded processors. Our technique achieves an order of magnitude lower power overhead compared to other similar techniques. Furthermore, our implementation of the developed framework has a low intrusion detection latency, which enables us to verify the control flow integrity of the executing code before the violating control flow instructions are retired from the processor pipeline.
{"title":"Stream cipher hash based execution monitoring (SCHEM) framework for intrusion detection on embedded processors","authors":"A. Chaudhari, J. Abraham","doi":"10.1109/IOLTS.2012.6313864","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313864","url":null,"abstract":"Hardware based execution monitoring of applications holds the promise for an effective and tamper-proof solution for intrusion detection on processor. This paper presents a practical hardware based intrusion detection framework which uses stream cipher based hashing techniques for runtime control flow and instruction integrity monitoring. This framework enables accurate monitoring of the control flow of a process with an instruction level granularity. Additional hardware required for implementation of our framework has very low power and area overheads which makes it possible to practically implement execution monitoring even on embedded processors. Our technique achieves an order of magnitude lower power overhead compared to other similar techniques. Furthermore, our implementation of the developed framework has a low intrusion detection latency, which enables us to verify the control flow integrity of the executing code before the violating control flow instructions are retired from the processor pipeline.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131468262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313853
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, A. Todri, A. Virazel, A. Touboul, F. Wrobel, F. Saigné
Electronic system reliability over soft errors is very critical as the transistor size shrinks. Many recent works have defined the device error rate under radiation for SRAMs in hold mode (static) and during operation (dynamic). This paper evaluates the impact of running test algorithms on SRAMs exposed to neutron radiation in order to define their stressing factor. The results that we show are based on experiments performed at the TSL facility in Uppsala, Sweden using a Quasi-Monoenergetic neutron beam. The evaluation of the test algorithms is based on the calculated device SEU cross section.
{"title":"Evaluation of test algorithms stress effect on SRAMs under neutron radiation","authors":"G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, A. Todri, A. Virazel, A. Touboul, F. Wrobel, F. Saigné","doi":"10.1109/IOLTS.2012.6313853","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313853","url":null,"abstract":"Electronic system reliability over soft errors is very critical as the transistor size shrinks. Many recent works have defined the device error rate under radiation for SRAMs in hold mode (static) and during operation (dynamic). This paper evaluates the impact of running test algorithms on SRAMs exposed to neutron radiation in order to define their stressing factor. The results that we show are based on experiments performed at the TSL facility in Uppsala, Sweden using a Quasi-Monoenergetic neutron beam. The evaluation of the test algorithms is based on the calculated device SEU cross section.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117294230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313866
E. Amat, A. Asenov, R. Canal, B. Cheng, J.-Ll. Cruz, Z. Jaksic, M. Corbalan, A. Rubio, P. Zuber
Summary form only given. Due to increased leakage currents and variability, classical bulk technology is reaching its scaling limits and some alternatives must be found. FinFETs are one of those alternatives. Through their 3D structure, they achieve better channel control which is the key to scalability. However, some sources of variability still remain. The impact of this technology shift on SRAM and DRAM memories is analyzed in this work.
{"title":"Analysis of FinFET technology on memories","authors":"E. Amat, A. Asenov, R. Canal, B. Cheng, J.-Ll. Cruz, Z. Jaksic, M. Corbalan, A. Rubio, P. Zuber","doi":"10.1109/IOLTS.2012.6313866","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313866","url":null,"abstract":"Summary form only given. Due to increased leakage currents and variability, classical bulk technology is reaching its scaling limits and some alternatives must be found. FinFETs are one of those alternatives. Through their 3D structure, they achieve better channel control which is the key to scalability. However, some sources of variability still remain. The impact of this technology shift on SRAM and DRAM memories is analyzed in this work.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114070096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313856
Zhen Gao, Wenhui Yang, Xiang Chen, Ming Zhao, Jing Wang
Relative to the Triple Modular Redundancy (TMR) scheme, the arithmetic residue codes based fault-tolerant DSP design consumes much less resources. However, the price for the low resource consumption is the fault missing problem. The basic tradeoff is that, smaller modulus used for the fault checking consumes fewer resources, but the fault missing rate is higher. The relationship between the value of modulus and the fault missing rate is analyzed theoretically in this paper for fault-tolerant FIR filter design, and the results are verified by FPGA implemented fault injections.
{"title":"Fault missing rate analysis of the arithmetic residue codes based fault-tolerant FIR filter design","authors":"Zhen Gao, Wenhui Yang, Xiang Chen, Ming Zhao, Jing Wang","doi":"10.1109/IOLTS.2012.6313856","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313856","url":null,"abstract":"Relative to the Triple Modular Redundancy (TMR) scheme, the arithmetic residue codes based fault-tolerant DSP design consumes much less resources. However, the price for the low resource consumption is the fault missing problem. The basic tradeoff is that, smaller modulus used for the fault checking consumes fewer resources, but the fault missing rate is higher. The relationship between the value of modulus and the fault missing rate is analyzed theoretically in this paper for fault-tolerant FIR filter design, and the results are verified by FPGA implemented fault injections.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116137574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313849
A. Evans, M. Nicolaidis, Shi-Jie Wen, D. Alexandrescu, Enrico Costenaro
In this paper, a new standard language called RIIF (Reliability Information Interchange Format) is defined which enables designers to specify the failure characteristics and reliability requirements for simple and complex components. This language enables EDA tools to analyze reliability models and to compute the failure rates for complex systems. A formal language makes it possible for suppliers and consumers to exchange reliability information in a consistent fashion and to use this information to build accurate reliability models. The RIIF language is a general purpose reliability modeling language and is not tied to a specific application domain or implementation technology.
{"title":"RIIF - Reliability information interchange format","authors":"A. Evans, M. Nicolaidis, Shi-Jie Wen, D. Alexandrescu, Enrico Costenaro","doi":"10.1109/IOLTS.2012.6313849","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313849","url":null,"abstract":"In this paper, a new standard language called RIIF (Reliability Information Interchange Format) is defined which enables designers to specify the failure characteristics and reliability requirements for simple and complex components. This language enables EDA tools to analyze reliability models and to compute the failure rates for complex systems. A formal language makes it possible for suppliers and consumers to exchange reliability information in a consistent fashion and to use this information to build accurate reliability models. The RIIF language is a general purpose reliability modeling language and is not tied to a specific application domain or implementation technology.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131197801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313869
D. Alexandrescu, Enrico Costenaro
Single Event Effects strongly impact the reliability of electronic circuits and systems, requiring careful SER characterization and adequately sized mitigation strategy. The SER study aims at providing relevant information about the circuit behavior in the specified working environment, in terms of Functional Failures rates, criticality and so on. Ultimately, the error mitigation efforts are directed at improving the function of the circuit in the presence of SEE by either reducing the failure occurrence rate or the failure impact. However, when dealing with SEEs affecting highly sophisticated electronic designs, functional issues are one of the most complex aspects to reliably characterize. This paper aims at proposing and evaluating several fault characterization techniques, meant to approximate the functional failures induced by Single Event Upsets in complex circuits, very early in the design flow. The two main contributions of our efforts consist in a differential fault simulation approach based on standard simulation tools and a novel parallel, SEE-optimized, stand-alone simulation tool. Both methods accurately evaluate the immediate propagation of SEE-induced faults and predict the long-term behavior of the faulty circuit running a specified application. The works described in this paper also benefit from various optimization techniques targeting lower simulation costs (in terms of CPU and man-power) while preserving the accuracy of the results. Ultimately, the results of each method compare positively with reference data obtained from an exhaustive fault simulation campaign. This encouraging outcome suggests that we can reliably obtain highly informative functional error information while spending reasonable resources (CPU, man-power, time).
{"title":"Towards optimized functional evaluation of SEE-induced failures in complex designs","authors":"D. Alexandrescu, Enrico Costenaro","doi":"10.1109/IOLTS.2012.6313869","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313869","url":null,"abstract":"Single Event Effects strongly impact the reliability of electronic circuits and systems, requiring careful SER characterization and adequately sized mitigation strategy. The SER study aims at providing relevant information about the circuit behavior in the specified working environment, in terms of Functional Failures rates, criticality and so on. Ultimately, the error mitigation efforts are directed at improving the function of the circuit in the presence of SEE by either reducing the failure occurrence rate or the failure impact. However, when dealing with SEEs affecting highly sophisticated electronic designs, functional issues are one of the most complex aspects to reliably characterize. This paper aims at proposing and evaluating several fault characterization techniques, meant to approximate the functional failures induced by Single Event Upsets in complex circuits, very early in the design flow. The two main contributions of our efforts consist in a differential fault simulation approach based on standard simulation tools and a novel parallel, SEE-optimized, stand-alone simulation tool. Both methods accurately evaluate the immediate propagation of SEE-induced faults and predict the long-term behavior of the faulty circuit running a specified application. The works described in this paper also benefit from various optimization techniques targeting lower simulation costs (in terms of CPU and man-power) while preserving the accuracy of the results. Ultimately, the results of each method compare positively with reference data obtained from an exhaustive fault simulation campaign. This encouraging outcome suggests that we can reliably obtain highly informative functional error information while spending reasonable resources (CPU, man-power, time).","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126529173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313851
E. Böhl, Markus Ihle
True random number generators (TRNGs) are used for cryptographic operations. By the use of TRNGs secret keys can be generated and the design can be made robust against attacks. In order to simplify further attacks the adversary tries to introduce some bias in the probability distribution of the TRNG output. A possibility to detect such attacks is shown in this paper. In difference to the most former publications all investigations are performed taking into account realistic technology parameters and parasitics.
{"title":"A fault attack robust TRNG","authors":"E. Böhl, Markus Ihle","doi":"10.1109/IOLTS.2012.6313851","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313851","url":null,"abstract":"True random number generators (TRNGs) are used for cryptographic operations. By the use of TRNGs secret keys can be generated and the design can be made robust against attacks. In order to simplify further attacks the adversary tries to introduce some bias in the probability distribution of the TRNG output. A possibility to detect such attacks is shown in this paper. In difference to the most former publications all investigations are performed taking into account realistic technology parameters and parasitics.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130410770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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