H. Ambrosius, X. Leijtens, T. de Vries, J. Bolk, E. Smalbrugge, M. Smit
{"title":"A Generic InP-based Photonic Integration Technology","authors":"H. Ambrosius, X. Leijtens, T. de Vries, J. Bolk, E. Smalbrugge, M. Smit","doi":"10.1109/OECC.2012.6276483","DOIUrl":null,"url":null,"abstract":"This paper describes a Generic InP-based Photonic Integration Technology that enables fabrication of a large variety of active- as well as passive circuits. In the COBRA clean room in Eindhoven a robust modular process flow is developed which consists of more than 10 depositions (including epitaxial growth), about 10 lithography steps (depending on the design) and more than 20 dry and wet etching steps. This process can be used to fabricate different circuits on one wafer in so-called multi-project wafer runs which allows a drastic reduction of the fabrication costs making even small- volume production economically feasible.","PeriodicalId":371480,"journal":{"name":"IPRM 2011 - 23rd International Conference on Indium Phosphide and Related Materials","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IPRM 2011 - 23rd International Conference on Indium Phosphide and Related Materials","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/OECC.2012.6276483","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This paper describes a Generic InP-based Photonic Integration Technology that enables fabrication of a large variety of active- as well as passive circuits. In the COBRA clean room in Eindhoven a robust modular process flow is developed which consists of more than 10 depositions (including epitaxial growth), about 10 lithography steps (depending on the design) and more than 20 dry and wet etching steps. This process can be used to fabricate different circuits on one wafer in so-called multi-project wafer runs which allows a drastic reduction of the fabrication costs making even small- volume production economically feasible.