Modeling and characterization of LDD and LDSD NMOS transistors

Conference Record of the 1993 IEEE Industry Applications Conference Twenty-Eighth IAS Annual Meeting Pub Date : 1993-10-02 DOI:10.1109/IAS.1993.299047

M.I. Castro Simas, J. Costa Freire, S. Finco, F. Behrens

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引用次数: 3

Abstract

Medium-voltage lateral structures for power NMOS devices, suitable for integration with standard low-voltage CMOS control circuits in power ICs, are presented. Two device types were fabricated on 1.5- mu m micron, N-well, two-metal-layer, 10-mask CMOS standard technology. Design rules and device mask geometry were adapted for enlarging the operating voltage range beyond 5 V. The LDD (lightly doped drain) NMOS transistor is based on the LDD concept. The LDSD (light doped source drain) NMOS transistor applies the same concept to both source and drain terminals. On-resistance as low as 9 m Omega cm/sup 2/ and breakdown voltages of 20 V were experimentally obtained. Monolithic integration of multiple switches with low-voltage control is possible, since structures are electrically compatible. The electric characterization and proposed model for LDD and LDSD NMOS devices in commutation are presented. These structures are aimed at smart power ICs using standard CMOS technologies, for low power applications. Experimental results are presented.<>

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LDD和LDSD NMOS晶体管的建模和表征

提出了功率NMOS器件的中压横向结构，适合与功率集成电路中的标准低压CMOS控制电路集成。采用1.5 μ m微米、n阱、双金属层、10掩模CMOS标准工艺制备了两种器件。设计规则和器件掩模几何适应扩大工作电压范围超过5 V。LDD(轻掺杂漏极)NMOS晶体管是基于LDD的概念。LDSD(光掺杂源漏极)NMOS晶体管将相同的概念应用于源极和漏极端。导通电阻低至9 m ω cm/sup 2/，击穿电压为20 V。多个开关与低压控制的单片集成是可能的，因为结构是电气兼容的。介绍了lddd和LDSD NMOS器件在换相中的电特性和所提出的模型。这些结构旨在使用标准CMOS技术的智能功率ic，用于低功耗应用。给出了实验结果。

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Conference Record of the 1993 IEEE Industry Applications Conference Twenty-Eighth IAS Annual Meeting

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