Built-in TPG with designed phaseshifts

D. Kagaris
{"title":"Built-in TPG with designed phaseshifts","authors":"D. Kagaris","doi":"10.1109/VTEST.2003.1197676","DOIUrl":null,"url":null,"abstract":"In this paper, we present built-in test pattern generation (TPG) mechanisms that can enforce a prescribed exact set of phaseshifts, or channel separations, on the bit sequences produced by their successive stages, while still requiring low hardware overhead. Such mechanisms are used in controlling the amount of correlations and/or linear dependencies that are problematic for pseudorandom and pseudoexhaustive TPG in a two-dimensional TPG architecture. The reduction in hardware overhead is achieved by a new technique that merges the logic of the original TPG mechanism with that of the required phase shifter network in order to yield an improved compact structure.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 21st VLSI Test Symposium, 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.2003.1197676","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12

Abstract

In this paper, we present built-in test pattern generation (TPG) mechanisms that can enforce a prescribed exact set of phaseshifts, or channel separations, on the bit sequences produced by their successive stages, while still requiring low hardware overhead. Such mechanisms are used in controlling the amount of correlations and/or linear dependencies that are problematic for pseudorandom and pseudoexhaustive TPG in a two-dimensional TPG architecture. The reduction in hardware overhead is achieved by a new technique that merges the logic of the original TPG mechanism with that of the required phase shifter network in order to yield an improved compact structure.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
内置TPG与设计相移
在本文中,我们提出了内置的测试模式生成(TPG)机制,该机制可以在由其连续阶段产生的位序列上强制执行规定的精确相移集或信道分离,同时仍然需要低硬件开销。这种机制用于控制二维TPG体系结构中对伪随机和伪穷举TPG有问题的相关性和/或线性依赖性的数量。硬件开销的减少是通过一种新技术实现的,该技术将原始TPG机制的逻辑与所需移相器网络的逻辑相结合,以产生改进的紧凑结构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
An efficient test relaxation technique for synchronous sequential circuits Fault testing for reversible circuits Test data compression using dictionaries with fixed-length indices [SOC testing] Building yield into systems-on chips for nanometer technologies Efficient seed utilization for reseeding based compression [logic testing]
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1