{"title":"A study on W vacancy defect in mono-layer transition-metal dichalcogenide (TMD) TFETs through systematic ab initio calculations","authors":"Jixuan Wu, Z. Fan, Jiezhi Chen, Xiangwei Jiang","doi":"10.23919/SNW.2017.8242271","DOIUrl":null,"url":null,"abstract":"Aiming at performance enhancements and robust reliability design of mono-layer transition-metal dichalcogenide (TMD) tunneling FET(TFET), W vacancy(V<inf>w</inf>) defect is systematically studied in this work. Impacts of V<inf>w</inf> defect's positions are characterized in WSe<inf>2</inf> TTETs by using rigorous ab initio simulations. It is found that V<inf>w</inf> defect that locates in the tunnel junction will increase I<inf>on</inf>, while it has no impact on T<inf>off</inf>. Further discussions are also made with focus on the variation of defect position in TFET and the fluctuations of device performance for robust circuit design.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Silicon Nanoelectronics Workshop (SNW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/SNW.2017.8242271","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Aiming at performance enhancements and robust reliability design of mono-layer transition-metal dichalcogenide (TMD) tunneling FET(TFET), W vacancy(Vw) defect is systematically studied in this work. Impacts of Vw defect's positions are characterized in WSe2 TTETs by using rigorous ab initio simulations. It is found that Vw defect that locates in the tunnel junction will increase Ion, while it has no impact on Toff. Further discussions are also made with focus on the variation of defect position in TFET and the fluctuations of device performance for robust circuit design.