Reducing power dissipation during at-speed test application

Abstract

Presents an approach to reducing power dissipation during at-speed test application. Based on re-ordering of the test-pair sequences, the switching activities of the circuit-under-test during test application can be minimized. Hamming distance between test-pairs is defined to guide test-pair re-ordering. It minimizes power dissipation during test application without reducing delay fault coverage. Experimental results are presented to demonstrate a reduction of power dissipation during test application in the range from 84.69 to 98.08%.