{"title":"Reduction of off-state leakage current on fully depleted DG-MOSFETs","authors":"Saji Joseph, George James, T. Mathew","doi":"10.1109/ELECTRO.2009.5441150","DOIUrl":null,"url":null,"abstract":"This paper will discuss the analysis and reduction of off-state leakage current on DG MOSFETs. We examine the influence of channel length (Lg) and channel thickness (Tsi) on device performance of nanoscale Double Gate (DG) MOSFETs, employing Non-equilibrium Green's function (NEGF) formalism. When the channel length is shrinks down, the electrostatic controllability of the gate over the channel decreases due to the increased charge sharing from source/drain. The present work provides design insights into the performance of nanoscale DG-MOSFET devices with optimal channel engineering and serves as a tool to optimize important device and technological parameters for 10–24′nm range.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELECTRO.2009.5441150","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper will discuss the analysis and reduction of off-state leakage current on DG MOSFETs. We examine the influence of channel length (Lg) and channel thickness (Tsi) on device performance of nanoscale Double Gate (DG) MOSFETs, employing Non-equilibrium Green's function (NEGF) formalism. When the channel length is shrinks down, the electrostatic controllability of the gate over the channel decreases due to the increased charge sharing from source/drain. The present work provides design insights into the performance of nanoscale DG-MOSFET devices with optimal channel engineering and serves as a tool to optimize important device and technological parameters for 10–24′nm range.
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