A low power based partitioning and binding technique for single chip application specific DSP architectures

Abstract

In this paper, we present a low power targeted high-level synthesis framework for the synthesis of single chip Application Specific DSP (Digital Signal Processing) architectures. This new framework is based on minimizing the switching activity on the functional units as well as the global buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for partitioning the given data flow graph describing the DSP algorithm. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs.