Pub Date : 1998-11-01DOI: 10.1109/ICISS.1997.630242
V. Bohossian, P. Hasler, Jehoshua Bruck
Circuits of threshold elements (Boolean input, Boolean output neurons) have been shown to be surprisingly powerful. Useful functions such as XOR, ADD and MULTIPLY can be implemented by such circuits more efficiently than by traditional AND/OR circuits. In view of that, we have designed and built a programmable threshold element. The weights are stored on polysilicon floating gates, providing long-term retention without refresh. The weight value is increased using tunneling and decreased via hot electron injection. A weight is stored on a single transistor allowing the development of dense arrays of threshold elements. A 16-input programmable neuron was fabricated in the standard 2 /spl mu/m double-poly analog process available from MOSIS. A long term goal of this research is to incorporate programmable threshold elements, as building blocks in Field Programmable Gate Arrays.
{"title":"Programmable neural logic","authors":"V. Bohossian, P. Hasler, Jehoshua Bruck","doi":"10.1109/ICISS.1997.630242","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630242","url":null,"abstract":"Circuits of threshold elements (Boolean input, Boolean output neurons) have been shown to be surprisingly powerful. Useful functions such as XOR, ADD and MULTIPLY can be implemented by such circuits more efficiently than by traditional AND/OR circuits. In view of that, we have designed and built a programmable threshold element. The weights are stored on polysilicon floating gates, providing long-term retention without refresh. The weight value is increased using tunneling and decreased via hot electron injection. A weight is stored on a single transistor allowing the development of dense arrays of threshold elements. A 16-input programmable neuron was fabricated in the standard 2 /spl mu/m double-poly analog process available from MOSIS. A long term goal of this research is to incorporate programmable threshold elements, as building blocks in Field Programmable Gate Arrays.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"65 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120942685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/ICISS.1997.630279
A. Henning, J. Firch, James M. Harris, E. B. Dehan, Bradford A. Cozad, L. Christel, Y. Fathi, D. Hopkins, L. Lilly, Wendell Mcculley, W. Weber, M. Zdeblick
The advent of MEMS (microelectromechanical systems) will enable dramatic changes in MEMS-based devices offer opportunities to achieve higher with decreased size and increased reliability. In this work, we describe the achievement of several important devices for use in the semiconductor equipment industry. They include a low-flow mass flow controller, a high-precision pressure regulator, and an integrated gas panel. Compared to current technology, the devices are ultra-small in size, thus minimizing dead volumes and gas contact surface areas. With wettable surfaces comprised of ceramic and silicon (or, silicon coated with Si/sub 3/N/sub 4/ or SiC), they are resistant to corrosion, and generate virtually no particles. The devices are created from modular components. The science and technology of these components will be detailed. The modules examined are: normally-open proportional valves; normally-closed, low leak-rate shut-off valves; critical orifices (to extract information of flow rate); flow models (to extract flow rate from pressure and temperature information); silicon-based pressure sensors; and, the precision ceramic-based packages which integrate these modules into useful devices for semiconductor processing. The work finishes with a detailed description of the low-flow mass flow controller.
{"title":"Microfluidic MEMS for semiconductor processing","authors":"A. Henning, J. Firch, James M. Harris, E. B. Dehan, Bradford A. Cozad, L. Christel, Y. Fathi, D. Hopkins, L. Lilly, Wendell Mcculley, W. Weber, M. Zdeblick","doi":"10.1109/ICISS.1997.630279","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630279","url":null,"abstract":"The advent of MEMS (microelectromechanical systems) will enable dramatic changes in MEMS-based devices offer opportunities to achieve higher with decreased size and increased reliability. In this work, we describe the achievement of several important devices for use in the semiconductor equipment industry. They include a low-flow mass flow controller, a high-precision pressure regulator, and an integrated gas panel. Compared to current technology, the devices are ultra-small in size, thus minimizing dead volumes and gas contact surface areas. With wettable surfaces comprised of ceramic and silicon (or, silicon coated with Si/sub 3/N/sub 4/ or SiC), they are resistant to corrosion, and generate virtually no particles. The devices are created from modular components. The science and technology of these components will be detailed. The modules examined are: normally-open proportional valves; normally-closed, low leak-rate shut-off valves; critical orifices (to extract information of flow rate); flow models (to extract flow rate from pressure and temperature information); silicon-based pressure sensors; and, the precision ceramic-based packages which integrate these modules into useful devices for semiconductor processing. The work finishes with a detailed description of the low-flow mass flow controller.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114662904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-08DOI: 10.1109/ICISS.1997.630255
M. Michalicek, J. Comtois, C. C. Barren
This paper describes the design and characterization of several types of micromirror devices to include process capabilities, device modeling, and test data resulting in deflection versus applied potential curves. These micromirror devices are the first to be fabricated in the state-of-the-art four-level planarized polysilicon process available at Sandia National Laboratories known as the Sandia Ultra-planar Multi-level MEMS Technology (SUMMiT). This enabling process permits the development of micromirror devices with near-ideal characteristics which have previously been unrealizable in standard three-layer polysilicon processes. This paper describes such characteristics as elevated address electrodes, individual address wiring beneath the device, planarized mirror surfaces using Chemical Mechanical Polishing (CMP), unique post-process metallization, and the best active surface area to date. This paper presents the design, fabrication, modeling, and characterization of several variations of Flexure-Beam (FBMD) and Axial-Rotation Micromirror Devices (ARMD). The released devices are first metallized using a standard sputtering technique relying on metallization guards and masks that are fabricated next to the devices. Such guards are shown to enable the sharing of bond pads between numerous arrays of micromirrors in order to maximize the number of on-chip test arrays. The devices are modeled and then empirically characterized using a laser interferometer setup located at the Air Force Institute of Technology (AFIT) at Wright-Patterson AFB in Dayton, Ohio. Unique design considerations for these micromirror devices and the SUMMiT process are also discussed. The models are then compared with the empirical data to produce a complete characterization of the devices in a deflection versus applied potential curve.
{"title":"Design and characterization of next-generation micromirrors fabricated in a four-level, planarized surface-micromachined polycrystalline silicon process","authors":"M. Michalicek, J. Comtois, C. C. Barren","doi":"10.1109/ICISS.1997.630255","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630255","url":null,"abstract":"This paper describes the design and characterization of several types of micromirror devices to include process capabilities, device modeling, and test data resulting in deflection versus applied potential curves. These micromirror devices are the first to be fabricated in the state-of-the-art four-level planarized polysilicon process available at Sandia National Laboratories known as the Sandia Ultra-planar Multi-level MEMS Technology (SUMMiT). This enabling process permits the development of micromirror devices with near-ideal characteristics which have previously been unrealizable in standard three-layer polysilicon processes. This paper describes such characteristics as elevated address electrodes, individual address wiring beneath the device, planarized mirror surfaces using Chemical Mechanical Polishing (CMP), unique post-process metallization, and the best active surface area to date. This paper presents the design, fabrication, modeling, and characterization of several variations of Flexure-Beam (FBMD) and Axial-Rotation Micromirror Devices (ARMD). The released devices are first metallized using a standard sputtering technique relying on metallization guards and masks that are fabricated next to the devices. Such guards are shown to enable the sharing of bond pads between numerous arrays of micromirrors in order to maximize the number of on-chip test arrays. The devices are modeled and then empirically characterized using a laser interferometer setup located at the Air Force Institute of Technology (AFIT) at Wright-Patterson AFB in Dayton, Ohio. Unique design considerations for these micromirror devices and the SUMMiT process are also discussed. The models are then compared with the empirical data to produce a complete characterization of the devices in a deflection versus applied potential curve.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123679485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-08DOI: 10.1109/ICISS.1997.630263
L. Pesando, B. Bostica, M. Burzio, F. Delpiano, P. Pellegrino
Parallel optical interconnections allow for a substantial improvement in the capacity of systems associating an high bit-rate for each channel with a consistent reduction in the number of cables needed for interconnecting different system parts, such as boards or cabinets. We constructed a 10 channel parallel optical transmitter with 12.5 Gbit/s total bit-rate. The silicon CMOS (Complementary Metal Oxide Semiconductor) laser driver Integrated Circuit (IC), completely designed in CSELT, allows for low power consumption and low-cost even at the high bit-rate achieved with this device. The module as a metal package pigtailed with a 50/125 mm fibre ribbon with standard MPO/sup TM//MTP/sup TM/ push-pull multifibre connector. The laser array is a low threshold edge emitting Fabry-Perot commercial device with /spl lambda/=1.3 /spl mu/m, which makes it suitable for the fibres used in the telecom networks. During thorough lab tests the module has been operated up to 1.25 Gbit/s/ch with a good performance in terms of BER (Bit Error Ratio) characteristic, better than 10/sup 14/, with a power budget of more than 10 dB and an overall power consumption of 1.3 W. The interconnection distance has been proven to be more than 500 m with a residual power margin of 4 dB with satisfactory BER figures.
{"title":"High bit-rate 10 channel optical transmitter for sub-system interconnection","authors":"L. Pesando, B. Bostica, M. Burzio, F. Delpiano, P. Pellegrino","doi":"10.1109/ICISS.1997.630263","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630263","url":null,"abstract":"Parallel optical interconnections allow for a substantial improvement in the capacity of systems associating an high bit-rate for each channel with a consistent reduction in the number of cables needed for interconnecting different system parts, such as boards or cabinets. We constructed a 10 channel parallel optical transmitter with 12.5 Gbit/s total bit-rate. The silicon CMOS (Complementary Metal Oxide Semiconductor) laser driver Integrated Circuit (IC), completely designed in CSELT, allows for low power consumption and low-cost even at the high bit-rate achieved with this device. The module as a metal package pigtailed with a 50/125 mm fibre ribbon with standard MPO/sup TM//MTP/sup TM/ push-pull multifibre connector. The laser array is a low threshold edge emitting Fabry-Perot commercial device with /spl lambda/=1.3 /spl mu/m, which makes it suitable for the fibres used in the telecom networks. During thorough lab tests the module has been operated up to 1.25 Gbit/s/ch with a good performance in terms of BER (Bit Error Ratio) characteristic, better than 10/sup 14/, with a power budget of more than 10 dB and an overall power consumption of 1.3 W. The interconnection distance has been proven to be more than 500 m with a residual power margin of 4 dB with satisfactory BER figures.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"18 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116753228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-08DOI: 10.1109/ICISS.1997.630262
H. Kurino, T. Matsumoto, K. Yu, N. Miyakawa, H. Itani, H. Tsukamoto, M. Koyanagi
It becomes possible to achieve the real time micro-vision system with extremely high image processing speed if three-dimensional LSI comes into reality because a higher level of parallel processing can be performed in three-dimensional LSI. Then, we have proposed a new three-dimensional integration technology for such real time micro-vision system with high image processing speed. Several key technologies for three-dimensional integration such as formation of buried interconnection and micro-bump, wafer thinning, wafer alignment and wafer bonding have been developed.
{"title":"Three-dimensional integration technology for real time micro-vision system","authors":"H. Kurino, T. Matsumoto, K. Yu, N. Miyakawa, H. Itani, H. Tsukamoto, M. Koyanagi","doi":"10.1109/ICISS.1997.630262","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630262","url":null,"abstract":"It becomes possible to achieve the real time micro-vision system with extremely high image processing speed if three-dimensional LSI comes into reality because a higher level of parallel processing can be performed in three-dimensional LSI. Then, we have proposed a new three-dimensional integration technology for such real time micro-vision system with high image processing speed. Several key technologies for three-dimensional integration such as formation of buried interconnection and micro-bump, wafer thinning, wafer alignment and wafer bonding have been developed.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128740399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-08DOI: 10.1109/ICISS.1997.630245
Y. Inoguchi, T. Matsuzawa, S. Horiguchi
This paper addresses the reconfiguration of Shifted Recursive Torus (SRT) network by considering thermo-radiation in stacked wafers implementation. The SRT networks are hierarchical torus networks and suitable for massively parallel systems. We propose fault-tolerance schemes for SRT networks to keep high network performance in stacked wafers implementation. The cooling of stacked wafers, however, is one of the most crucial problems for implementation of massively parallel systems. Two cooling approaches have been proposed for SRT in stacked implementation. Introducing a thermo-radiation model into SRT in stacked implementation, reconfiguration performance of SRT was evaluated. Comparing the system yields and the maximum temperatures, these cooling approaches can keep high system yield and lower temperature of 3D implementation.
{"title":"SRT interconnection network on 3D stacked implementation by considering thermo-radiation","authors":"Y. Inoguchi, T. Matsuzawa, S. Horiguchi","doi":"10.1109/ICISS.1997.630245","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630245","url":null,"abstract":"This paper addresses the reconfiguration of Shifted Recursive Torus (SRT) network by considering thermo-radiation in stacked wafers implementation. The SRT networks are hierarchical torus networks and suitable for massively parallel systems. We propose fault-tolerance schemes for SRT networks to keep high network performance in stacked wafers implementation. The cooling of stacked wafers, however, is one of the most crucial problems for implementation of massively parallel systems. Two cooling approaches have been proposed for SRT in stacked implementation. Introducing a thermo-radiation model into SRT in stacked implementation, reconfiguration performance of SRT was evaluated. Comparing the system yields and the maximum temperatures, these cooling approaches can keep high system yield and lower temperature of 3D implementation.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129265435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-08DOI: 10.1109/ICISS.1997.630240
V. K. Prasanna
Summary form only given. Advances in semiconductor technology have led to many devices in which the computing devices can be configured as the computation proceeds. Field Programmable Gate Arrays is a typical commercially available configurable device. Such configurability offers several opportunities to speed-up computations. However, algorithmic innovations are needed to exploit such features to obtain fast parallel solutions. This talk will introduce and illustrate algorithmic configurable computing and contrast it with traditional approach based on logic synthesis. This talk will begin with the theoretical foundations of such computations by introducing the Reconfigurable Mesh model that was defined by USC researchers and others several years ago. Dynamic reconfiguration, in which the connections are changed as the computation proceeds is a powerful mechanism to achieve fast parallel solutions. We will illustrate the power of dynamic reconfiguration using this abstract model and show how scalable and portable solutions can be designed using currently available devices which offer limited configurability. These ideas will be illustrated by a number of examples from the USC MAARC project.
{"title":"The power of dynamic reconfiguration","authors":"V. K. Prasanna","doi":"10.1109/ICISS.1997.630240","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630240","url":null,"abstract":"Summary form only given. Advances in semiconductor technology have led to many devices in which the computing devices can be configured as the computation proceeds. Field Programmable Gate Arrays is a typical commercially available configurable device. Such configurability offers several opportunities to speed-up computations. However, algorithmic innovations are needed to exploit such features to obtain fast parallel solutions. This talk will introduce and illustrate algorithmic configurable computing and contrast it with traditional approach based on logic synthesis. This talk will begin with the theoretical foundations of such computations by introducing the Reconfigurable Mesh model that was defined by USC researchers and others several years ago. Dynamic reconfiguration, in which the connections are changed as the computation proceeds is a powerful mechanism to achieve fast parallel solutions. We will illustrate the power of dynamic reconfiguration using this abstract model and show how scalable and portable solutions can be designed using currently available devices which offer limited configurability. These ideas will be illustrated by a number of examples from the USC MAARC project.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130174300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-08DOI: 10.1109/ICISS.1997.630266
Y. Lee, V. Jain
This paper presents an efficient VLSI Architecture for an advanced Direct Sequence CDMA Wireless Communication Receiver. Compensating for near/far effects is critical for the satisfactory performance of D/S CDMA systems. An effective approach to combat the near/far effect is multi-user detection. This approach has the potential of increasing the capacity by canceling co-channel interference. The receiver discussed here operates by successively canceling user interferences ranked in order of received power levels. The ranking is obtained from the (magnitude of) the correlations of user chip sequences with the received signal. We present an efficient VLSI architecture for its implementation. Further, we show that the performance of this receiver is vastly superior to the conventional receiver (without cancellation).
{"title":"VLSI architecture for an advance DS/CDMA wireless communication receiver","authors":"Y. Lee, V. Jain","doi":"10.1109/ICISS.1997.630266","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630266","url":null,"abstract":"This paper presents an efficient VLSI Architecture for an advanced Direct Sequence CDMA Wireless Communication Receiver. Compensating for near/far effects is critical for the satisfactory performance of D/S CDMA systems. An effective approach to combat the near/far effect is multi-user detection. This approach has the potential of increasing the capacity by canceling co-channel interference. The receiver discussed here operates by successively canceling user interferences ranked in order of received power levels. The ranking is obtained from the (magnitude of) the correlations of user chip sequences with the received signal. We present an efficient VLSI architecture for its implementation. Further, we show that the performance of this receiver is vastly superior to the conventional receiver (without cancellation).","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"25 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117311915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-08DOI: 10.1109/ICISS.1997.630252
E. Kolesar, R. Reston
A miniature gas chromatography (GC) system has been designed and fabricated using silicon micromachining and integrated circuit (IC) processing techniques. The silicon micromachined gas chromatography system (SMGCS) is composed of a miniature sample injector that incorporates a 10 /spl mu/l sample loop; a 0.9-m long, rectangular-shaped (300 /spl mu/m width and 10 /spl mu/m height) capillary column coated with a 0.2-/spl mu/m thick copper phthalocyanine (CuPc) stationary-phase; and a dual-detector scheme based upon a CuPc-coated chemiresistor and a commercially available, 125-/spl mu/m diameter thermal conductivity detector (TCD) bead. Silicon micromachining was employed to fabricate the interface between the sample injector and the GC column, the column itself, and the dual-detector cavity. A novel IC thin-film processing technique was developed to sublime the CuPc stationary-phase coating on the column walls that were micromachined in the host silicon wafer substrate and Pyrex cover plate, which were then electrostatically bonded together. The SMGCS can separate binary gas mixtures composed of parts per-million (ppm) concentrations of ammonia (NH/sub 3/) and nitrogen dioxide (NO/sub 2/) when isothermally operated (55-80/spl deg/C). With a helium carrier gas and nitrogen diluent, a 10 /spl mu/l sample volume containing ammonia and nitrogen dioxide injected at 40 psi (2.8/spl times/10/sup 5/ Pa) can be separated in less than 30 minutes.
{"title":"Silicon micromachined gas chromatography system","authors":"E. Kolesar, R. Reston","doi":"10.1109/ICISS.1997.630252","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630252","url":null,"abstract":"A miniature gas chromatography (GC) system has been designed and fabricated using silicon micromachining and integrated circuit (IC) processing techniques. The silicon micromachined gas chromatography system (SMGCS) is composed of a miniature sample injector that incorporates a 10 /spl mu/l sample loop; a 0.9-m long, rectangular-shaped (300 /spl mu/m width and 10 /spl mu/m height) capillary column coated with a 0.2-/spl mu/m thick copper phthalocyanine (CuPc) stationary-phase; and a dual-detector scheme based upon a CuPc-coated chemiresistor and a commercially available, 125-/spl mu/m diameter thermal conductivity detector (TCD) bead. Silicon micromachining was employed to fabricate the interface between the sample injector and the GC column, the column itself, and the dual-detector cavity. A novel IC thin-film processing technique was developed to sublime the CuPc stationary-phase coating on the column walls that were micromachined in the host silicon wafer substrate and Pyrex cover plate, which were then electrostatically bonded together. The SMGCS can separate binary gas mixtures composed of parts per-million (ppm) concentrations of ammonia (NH/sub 3/) and nitrogen dioxide (NO/sub 2/) when isothermally operated (55-80/spl deg/C). With a helium carrier gas and nitrogen diluent, a 10 /spl mu/l sample volume containing ammonia and nitrogen dioxide injected at 40 psi (2.8/spl times/10/sup 5/ Pa) can be separated in less than 30 minutes.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124450228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-08DOI: 10.1109/ICISS.1997.630248
S. Steidl, S. Carlough, M. Ernest, A. Garg, R. Kraft, J. McDonald
Wafer Scale Hybrid Packages (WSHPs) or MultiChip Modules (MCMs) have provided a breakthrough in system packaging for high clock rate systems. Based on this technology a 2 GHz Fast RISC demonstration integer-only computational engine has been designed, and is submitted for fabrication. This design involved use of Heterojunction Bipolar Transistors (HBTs) in the GaAs/AlGaAs materials system. This paper reviews some of the schemes used in that design and shows how there are actually several paths using advanced GaAs/AlGaAs and SiGe HBT technology to create similar systems that can actually run 8 times faster. Some of the challenges facing the architect and chip designer are discussed.
{"title":"A 16 GHz fast RISC engine using GaAs/AlGaAs and SiGe HBT technology","authors":"S. Steidl, S. Carlough, M. Ernest, A. Garg, R. Kraft, J. McDonald","doi":"10.1109/ICISS.1997.630248","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630248","url":null,"abstract":"Wafer Scale Hybrid Packages (WSHPs) or MultiChip Modules (MCMs) have provided a breakthrough in system packaging for high clock rate systems. Based on this technology a 2 GHz Fast RISC demonstration integer-only computational engine has been designed, and is submitted for fabrication. This design involved use of Heterojunction Bipolar Transistors (HBTs) in the GaAs/AlGaAs materials system. This paper reviews some of the schemes used in that design and shows how there are actually several paths using advanced GaAs/AlGaAs and SiGe HBT technology to create similar systems that can actually run 8 times faster. Some of the challenges facing the architect and chip designer are discussed.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126175110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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