VLSI architecture of EBCOT Tier-2 encoder for JPEG2000

Abstract

This paper proposed a VLSI architecture of embedded block coding with optimized truncation (EBCOT) Tier-2 encoder for JPEG2000. Based on a rate-distortion (RD) slope method, the proposed architecture eliminate the iteration of the RD truncation, reduces the scale of the on-chip bit-stream buffering from full tile size down to three-code-block size and at the same time, accurately control the compression bit-rate with 95% precision. The proposed Tier-2 encoder has already been integrated into the JPEG2000 codec and fabricated with SMIC 0.18 /spl mu/m 1P6M CMOS technology.