6.2 A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss

Abstract

With the introduction of PAM-4 signaling at 56Gb/s and the decreased benefits of CMOS scaling for high-speed mixed-signal designs, SerDes designers and system architects are faced with severe performance versus power budget constraints. Power management and energy efficiency have become the main drivers for system design. However, industry standards such as EEE have failed to keep up with efficiency demands. In this context the choice between a so-called analog mixed signal (AMS) SerDes architecture vs. an ADC-DSP-based one has been debated at length. AMS provides significantly lower maximum power [2, 4] while ADC-DSP provides higher link margin [1] thus avoiding expensive and power hungry repeater ICs that largely negate the power advantage of AMS SerDes in a system. AMS provides an easier and cheaper approach to implement multi-tap DFEs [3] compared to DSP where it is typically very expensive to implement more than a 1-tap DFE. This paper will show an ADC-DSP SerDes transceiver with a 2-tap DFE is capable of operating error-free over a 38dB link yet having an overall power budget similar to AMS. The same basic SerDes architecture is implemented (Fig. 6.2.1) with minor differences in 16nm and 7nm FinFET, however, power scaling is incorporated into the 7nm version only.