{"title":"The design of high performance elliptic curve cryptographic","authors":"Jin-Hua Hong, Wei-Chung Wu","doi":"10.1109/MWSCAS.2009.5236038","DOIUrl":null,"url":null,"abstract":"In this paper, we propose an elliptic curve cryptographic (ECC) architecture for a lower hardware resource. In our work, the different paths of encryption and decryption could be chosen, and the elliptic curve (EC) is based on GF (2163). The EC scalar multiplication is a main operation module that includes add, Montgomery multiplier and inverse in ECC architecture. All modules are organized in a hierarchical structure according to their complexity. In the hardware implementations using a 0.18µ m TSMC cell library, a 69 K gate count is possessed, and the maximum speed is 181 MHz. The EC multiplication time is from 1.26 ms to 2.52 ms. The private key k is a 163-bit random number. If the private key k is chosen to be a small one, the EC multiplication time would be faster.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2009.5236038","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
In this paper, we propose an elliptic curve cryptographic (ECC) architecture for a lower hardware resource. In our work, the different paths of encryption and decryption could be chosen, and the elliptic curve (EC) is based on GF (2163). The EC scalar multiplication is a main operation module that includes add, Montgomery multiplier and inverse in ECC architecture. All modules are organized in a hierarchical structure according to their complexity. In the hardware implementations using a 0.18µ m TSMC cell library, a 69 K gate count is possessed, and the maximum speed is 181 MHz. The EC multiplication time is from 1.26 ms to 2.52 ms. The private key k is a 163-bit random number. If the private key k is chosen to be a small one, the EC multiplication time would be faster.