Logic synthesis of multi-output functions for PAL-based CPLDs

Abstract

In this paper multi-level synthesis for PAL-based CPLDs is presented. The essence of the method is to search for multi-output implicants that can be shared by several functions. This approach presents a unique form for illustrating a minimized form of a multi-output Boolean function. The presented method, implemented within the PALDec system, is based on the analysis of graph nodes that represent states of a digital circuit outputs. The results of synthesis for benchmarks are compared to the classical technology mapping method.