Hybrid dual-threshold design techniques for high-performance processors with low-power features

Abstract

This paper investigates delay, power and area of several critical library components for high-performance, low-power microprocessor designs. To improve performance of a 0.18-/spl mu/m technology at a supply voltage of 1.8 V, the proposed hybrid dual-V/sub t/ (HDVT) circuit architectures enhance speed of low-V/sub t/ by 21% while reducing leakage power dissipation of low-V/sub t/ by an order of magnitude for combinatorial logic. For sequential elements, a HDVT split-slave dual-path (HSSDP) and Push-Pull Isolation (HPPI) registers are proposed to improve 29-92% performance over an HDVT-conventional registers with 20-89% less energy consumption. For the datapath, a HDVT hierarchical, reduced-swing, dual-V/sub t/ logic (HHRSL) comparator is proposed to improve the delay of prior arts by up to 50%.