3D simulation of electrical characteristic fluctuation induced by interface traps at Si/high-к oxide interface and random dopants in 16-nm-Gate CMOS devices

Abstract

The random dopant (RD)-induced threshold voltage fluctuation (σVth) was explored recently [1–4]. RD fluctuation (RDF) has been one of challenges in nano-CMOS technologies; consequently, high-к/metal gate (HKMG) approach is adopted to suppress intrinsic parameter fluctuation and leakage current for sub-45-nm generations. However, random interface traps (ITs) appearing at Si/high-к oxide interface results in a new fluctuation source [2]. Effects of ITs and RDs on electrical characteristic fluctuation have not been explored yet. In this work, we study influences of random ITs and RDs on 16-nm CMOS devices using an experimentally calibrated 3D device simulation [1–4]. Devices with totally random ITs, RDs, and “ITs+RDs” (i.e., 3D device simulation with considering random ITs and RDs simultaneously) are generated and simulated to assess the device variability.