Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study

Abstract

Radiation effects still present a challenge even with the increased robustness of the multigate devices. The higher density of devices in a small area and the reduction on the node capacitance of the trend technologies keep the radiation robustness evaluation a key parameter on the circuit design, mainly targeting aerospace applications. These applications may also demand power-efficient design. Thus, it is relevant to consider the circuit behavior at different voltage levels of operation. This work provides an analysis of radiation effects on variations of a circuit-level benchmark in 7 nm FinFET device technology, intending to evaluate how the gate mapping affects the circuit susceptibility to radiation faults. Five different circuits were analyzed on supply voltages ranging from 0.7 V to 0.4 V. The LETth for all five circuits and their radiation robustness ranking were determined. The operation of the circuits below 0.5V introduces over 75% more sensitivity on the evaluated circuits. The results show that exploring gate mapping can be adopted to improve robustness. Adopting the NAND2 gate instead of NOR2 gate in the output improves the output robustness by about 38.6%. Moreover, exploring the transistor sizing only in the most sensitive gates can improve the robustness over to 69%.