Pub Date : 2021-10-27DOI: 10.1109/lats53581.2021.9651875
{"title":"[Copyright notice]","authors":"","doi":"10.1109/lats53581.2021.9651875","DOIUrl":"https://doi.org/10.1109/lats53581.2021.9651875","url":null,"abstract":"","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116595816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651807
A. Ruospo, Lucas Matana Luza, A. Bosio, Marcello Traiola, L. Dilillo, Ernesto Sánchez
In the last years, the adoption of Artificial Neural Networks (ANNs) in safety-critical applications has required an in-depth study of their reliability. For this reason, the research community has shown a growing interest in understanding the robustness of artificial computing models to hardware faults. Indeed, several recent studies have demonstrated that hardware faults induced by an external perturbation or due to silicon wear out and aging effects can significantly impact the ANN inference leading to wrong predictions. This work classifies and analyses the principal reliability assessment methodologies based on Fault Injection at different abstraction levels and with different procedures. Some of the most representative academic and industrial works proposed in the literature are described and the principal advantages, and drawbacks are highlighted.
{"title":"Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks","authors":"A. Ruospo, Lucas Matana Luza, A. Bosio, Marcello Traiola, L. Dilillo, Ernesto Sánchez","doi":"10.1109/LATS53581.2021.9651807","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651807","url":null,"abstract":"In the last years, the adoption of Artificial Neural Networks (ANNs) in safety-critical applications has required an in-depth study of their reliability. For this reason, the research community has shown a growing interest in understanding the robustness of artificial computing models to hardware faults. Indeed, several recent studies have demonstrated that hardware faults induced by an external perturbation or due to silicon wear out and aging effects can significantly impact the ANN inference leading to wrong predictions. This work classifies and analyses the principal reliability assessment methodologies based on Fault Injection at different abstraction levels and with different procedures. Some of the most representative academic and industrial works proposed in the literature are described and the principal advantages, and drawbacks are highlighted.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117001237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651889
Rafael N. M. Oliveira, F. A. D. Silva, Ricardo Reis, C. Meinhardt
This paper presents a comparative analysis of radiation sensitivity and SET mitigation techniques for the Mirror Full Adder topology implemented with FinFET devices at 7 nm node, considering nominal and near-threshold operation. The mitigation techniques investigated are Decoupling Cells and Transistor Sizing. Transistor Sizing may improved robustness up to $2mathrm{x}$ (nominal) and close to $3mathrm{x}$ (near-threshold). Combining the techniques decreases the total error occurrence close to 60% at nominal operation and up to 34% at near-threshold operation.
{"title":"SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology","authors":"Rafael N. M. Oliveira, F. A. D. Silva, Ricardo Reis, C. Meinhardt","doi":"10.1109/LATS53581.2021.9651889","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651889","url":null,"abstract":"This paper presents a comparative analysis of radiation sensitivity and SET mitigation techniques for the Mirror Full Adder topology implemented with FinFET devices at 7 nm node, considering nominal and near-threshold operation. The mitigation techniques investigated are Decoupling Cells and Transistor Sizing. Transistor Sizing may improved robustness up to $2mathrm{x}$ (nominal) and close to $3mathrm{x}$ (near-threshold). Combining the techniques decreases the total error occurrence close to 60% at nominal operation and up to 34% at near-threshold operation.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127915979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651805
Orlando Verducci, D. L. Oliveira, R. Moreno
Fault tolerance design is an increasing concern due to VLSI technology scaling, which implements more complex systems in a single chip. Each transistor in such systems is more susceptible to the effects of high-energy particle strikes, mainly in reduced power supply applications. Glitches in any node of the circuit caused by a soft error may propagate or even captured by a memory cell components. In FPGA, this issue is particularly concerning because, in such target devices, any digital circuitry is modeled using programmed LUTs (Look Up Tables) where a flipped bit cannot be recovered unless new programming on it. The proposed architecture for combinational circuits in FPGA devices enhances robustness to a QDI (Quasi-Delay Insensitive) digital design inserting a novel output register based on gates that validate each dual-rail variable the system according to the current processing cycle. The reduced penalties in area, power, and latency for the proposed fault-tolerant architecture are interesting compared to Triple Modular Redundancy (TMR), and Dual Modular Redundancy (DMR) approaches.
{"title":"Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices","authors":"Orlando Verducci, D. L. Oliveira, R. Moreno","doi":"10.1109/LATS53581.2021.9651805","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651805","url":null,"abstract":"Fault tolerance design is an increasing concern due to VLSI technology scaling, which implements more complex systems in a single chip. Each transistor in such systems is more susceptible to the effects of high-energy particle strikes, mainly in reduced power supply applications. Glitches in any node of the circuit caused by a soft error may propagate or even captured by a memory cell components. In FPGA, this issue is particularly concerning because, in such target devices, any digital circuitry is modeled using programmed LUTs (Look Up Tables) where a flipped bit cannot be recovered unless new programming on it. The proposed architecture for combinational circuits in FPGA devices enhances robustness to a QDI (Quasi-Delay Insensitive) digital design inserting a novel output register based on gates that validate each dual-rail variable the system according to the current processing cycle. The reduced penalties in area, power, and latency for the proposed fault-tolerant architecture are interesting compared to Triple Modular Redundancy (TMR), and Dual Modular Redundancy (DMR) approaches.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131748467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/lats53581.2021.9651854
{"title":"LATS2021 Committees","authors":"","doi":"10.1109/lats53581.2021.9651854","DOIUrl":"https://doi.org/10.1109/lats53581.2021.9651854","url":null,"abstract":"","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115402421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651751
Mohammadreza Rezaei, F. J. Franco, J. Fabero, H. Mecha, H. Puchner, J. A. Clemente
An experimental study on the SEU sensitivity of 65-nm, 90-nm, and 130-nm volatile bulk COTS SRAMs against thermal neutron irradiation while applying Dynamic Voltage Scaling (DVS) is presented. Results show a linear relation between the SEU cross-sections and Icc of the DUTs. Moreover, it is demonstrated that, even tough applying DVS increases the SEU cross-section, taking the power consumption into account, this approach is beneficial.
{"title":"Impact of DVS on Power Consumption and SEE Sensitivity of COTS Volatile SRAMs","authors":"Mohammadreza Rezaei, F. J. Franco, J. Fabero, H. Mecha, H. Puchner, J. A. Clemente","doi":"10.1109/LATS53581.2021.9651751","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651751","url":null,"abstract":"An experimental study on the SEU sensitivity of 65-nm, 90-nm, and 130-nm volatile bulk COTS SRAMs against thermal neutron irradiation while applying Dynamic Voltage Scaling (DVS) is presented. Results show a linear relation between the SEU cross-sections and Icc of the DUTs. Moreover, it is demonstrated that, even tough applying DVS increases the SEU cross-section, taking the power consumption into account, this approach is beneficial.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123132134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651794
J. Brum, T. K. Sartori, J. Lin, M. G. Trindade, H. Fourati, R. Velazco, R. P. Bastos
The space industry has been launching nanosatellites in order to reduce the weight of the payload and monitor space at a lower cost benefit than a conventional satellite. In this context, the use of Attitude Estimation (AE) algorithms have become more and more important. This paper evaluates the effectiveness of a processing system running an AE algorithm under an emulation-based fault injection campaign. This method is able to emulate soft errors directly in the development board's registers and allows to put in evidence critical situations, such as the wrong calculation of a reference component in space. Results and preliminary analysis suggest a predominance of matches in general-purpose registers and some failures in those called frame point, demanding extended fault injection campaign to identify further details.
{"title":"Evaluation of Attitude Estimation Algorithm under Soft Error Effects","authors":"J. Brum, T. K. Sartori, J. Lin, M. G. Trindade, H. Fourati, R. Velazco, R. P. Bastos","doi":"10.1109/LATS53581.2021.9651794","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651794","url":null,"abstract":"The space industry has been launching nanosatellites in order to reduce the weight of the payload and monitor space at a lower cost benefit than a conventional satellite. In this context, the use of Attitude Estimation (AE) algorithms have become more and more important. This paper evaluates the effectiveness of a processing system running an AE algorithm under an emulation-based fault injection campaign. This method is able to emulate soft errors directly in the development board's registers and allows to put in evidence critical situations, such as the wrong calculation of a reference component in space. Results and preliminary analysis suggest a predominance of matches in general-purpose registers and some failures in those called frame point, demanding extended fault injection campaign to identify further details.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"362 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115954295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651871
K. Coulié, H. Aziza, W. Rahajandraibe
Emerging non-volatile memories, based on resistive switching mechanisms and known as Resistive Random Access Memory (RRAM), are attractive candidates to overcome power, cost and integration density limitations of conventional memories. Moreover, RRAM has exhibited very good tolerance to radiation. In this context, this paper proposes to investigate Single Event Effects in RRAM memory arrays. The decoding circuitry of the memory array, including bit line and source line drivers is targeted. Currents generated by an ionizing particle crossing the memory array are first injected at specific nodes of the memory circuit. Their impact is evaluated by extracting the resistance state of each cell of the memory array before and after the ionizing particle strike. Worst cases scenarios are studied in order to point out the most sensitive configurations able to induce SEE.
{"title":"Investigation of Single Event Effects in a Resistive RAM memory array by SPICE level simulation","authors":"K. Coulié, H. Aziza, W. Rahajandraibe","doi":"10.1109/LATS53581.2021.9651871","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651871","url":null,"abstract":"Emerging non-volatile memories, based on resistive switching mechanisms and known as Resistive Random Access Memory (RRAM), are attractive candidates to overcome power, cost and integration density limitations of conventional memories. Moreover, RRAM has exhibited very good tolerance to radiation. In this context, this paper proposes to investigate Single Event Effects in RRAM memory arrays. The decoding circuitry of the memory array, including bit line and source line drivers is targeted. Currents generated by an ionizing particle crossing the memory array are first injected at specific nodes of the memory circuit. Their impact is evaluated by extracting the resistance state of each cell of the memory array before and after the ionizing particle strike. Worst cases scenarios are studied in order to point out the most sensitive configurations able to induce SEE.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122234329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651789
E. Brum, M. Fieback, T. Copetti, H. Jiayi, S. Hamdioui, F. Vargas, L. Bolzani
Over the last fifty years Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down, making the design of high-performance applications possible. However, there is a growing concern that device scaling will become infeasible below a certain feature size. In parallel, emerging applications present high demands regarding storage and computing capability, combined with challenging constraints. In this scenario, memristive devices have become promising candidates to replace or complement CMOS technology due to their CMOS manufacturing process compatibility, zero standby power consumption as well as high scalability and density. Despite these advantages, the implementation of high-density memories based on memristive devices poses some challenges related manufacturing process variation and consequently, to their reliability during lifetime. This paper investigates the impact of manufacturing process variation on Resistive Random Access Memories (RRAMs). In more detail, an evaluation of the RRAM's functionality when considering different levels of manufacturing process variation is performed. The obtained results show that different parameters can degrade the functionality of the RRAM cell as well as that there is a relation between the performed operating sequence and the tolerated percentage of variability. Finally, it is important to mention that understanding how process variation impacts the functionality of RRAM cells is considered essential to guarantee their reliability during lifetime, also allowing to optimize manufacturing processes.
{"title":"Evaluating the Impact of Process Variation on RRAMs","authors":"E. Brum, M. Fieback, T. Copetti, H. Jiayi, S. Hamdioui, F. Vargas, L. Bolzani","doi":"10.1109/LATS53581.2021.9651789","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651789","url":null,"abstract":"Over the last fifty years Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down, making the design of high-performance applications possible. However, there is a growing concern that device scaling will become infeasible below a certain feature size. In parallel, emerging applications present high demands regarding storage and computing capability, combined with challenging constraints. In this scenario, memristive devices have become promising candidates to replace or complement CMOS technology due to their CMOS manufacturing process compatibility, zero standby power consumption as well as high scalability and density. Despite these advantages, the implementation of high-density memories based on memristive devices poses some challenges related manufacturing process variation and consequently, to their reliability during lifetime. This paper investigates the impact of manufacturing process variation on Resistive Random Access Memories (RRAMs). In more detail, an evaluation of the RRAM's functionality when considering different levels of manufacturing process variation is performed. The obtained results show that different parameters can degrade the functionality of the RRAM cell as well as that there is a relation between the performed operating sequence and the tolerated percentage of variability. Finally, it is important to mention that understanding how process variation impacts the functionality of RRAM cells is considered essential to guarantee their reliability during lifetime, also allowing to optimize manufacturing processes.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122680133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651758
H. Aziza, K. Coulié, W. Rahajandraibe
Resistive RAM (RAM) intrinsic variability is widely recognized as a major hurdle for widespread adoption of the technology. Moreover, the deeper we go into the High Resistance State (HRS), the higher the variability. In this context, this paper proposes circuit level design strategies to mitigate HRS variability. During the RESET operation, the programming current is strictly controlled while the voltage across the RRAM cell is regulated. From a design standpoint, a write termination circuit is used to constantly sense the programming current and stop the RESET pulse when the preferred RESET current is reached. The write termination is combined with a voltage regulator which provides a strict control of the RESET voltage. The paper first reviews the RRAM variability phenomenon. Then, an optimized programming scheme is developed to control the HRS state to approach zero-variability. Compared to the classical fixed-pulse programming scheme, variability is reduced by 99%.
{"title":"Design Considerations Towards Zero-Variability Resistive RAMs in HRS State","authors":"H. Aziza, K. Coulié, W. Rahajandraibe","doi":"10.1109/LATS53581.2021.9651758","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651758","url":null,"abstract":"Resistive RAM (RAM) intrinsic variability is widely recognized as a major hurdle for widespread adoption of the technology. Moreover, the deeper we go into the High Resistance State (HRS), the higher the variability. In this context, this paper proposes circuit level design strategies to mitigate HRS variability. During the RESET operation, the programming current is strictly controlled while the voltage across the RRAM cell is regulated. From a design standpoint, a write termination circuit is used to constantly sense the programming current and stop the RESET pulse when the preferred RESET current is reached. The write termination is combined with a voltage regulator which provides a strict control of the RESET voltage. The paper first reviews the RRAM variability phenomenon. Then, an optimized programming scheme is developed to control the HRS state to approach zero-variability. Compared to the classical fixed-pulse programming scheme, variability is reduced by 99%.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116037072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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