16.9 4.48GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur

Michael Peter Kennedy, Yann Donnelly, James Breslin, Stefano Tulisi, Sanganagouda Patil, Ciaran Curtin, Stephen Brookes, Brian Shelly, P. Griffin, M. Keaveney
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引用次数: 8

Abstract

The instantaneous divide value of the multimodulus divider in the feedback path of a fractional-N PLL is determined by a divider controller, which is usually implemented as a digital delta-sigma modulator $(\mathrm (D)\Delta \Sigma \mathrm (M))$. A disadvantage of the fractional-N PLL is the presence of fractional spurs, which result from interaction between the signal introduced by the $(\mathrm (D)\Delta \Sigma \mathrm (M))$ and nonlinearities in the loop. When fractional spurs at frequencies close to integer boundaries lie inside the loop bandwidth, they cannot be attenuated by filtering. The Successive Requantizer (SR) is an alternative to the $(\mathrm (D)\Delta \Sigma \mathrm (M))$-based divider controller, which randomizes the quantization process more effectively than $(\mathrm (D)\Delta \Sigma \mathrm (M))$. Wang et al. reported a worst-case in-band fractional spur of -64dBc in a 2.4GHz charge-pump PLL [1]. Liang and Wang reported a -70dBc worst-case fractional spur in a 2GHz analog PLL with a hybrid VCO and $(\mathrm (D)\Delta \Sigma \mathrm (M))$-based divider controller [2]. Familier and Galton improved the performance of the SR by implementing higher-order noise shaping. They achieved a worst-case fractional spur of -72dBc in a 3.3GHz analog PLL with a third-order SR [3]. The SR quantizes the frequency-control word one bit at a time, and, therefore, requires n stages in the case of an n-bit modulus. Thirunarayanan et al. implemented a hybrid MASH-SR divider-controller structure using four SR quantization blocks [4]. The divider-controller architecture described in this paper enables a 4.48GHz analog PLL to exhibit an in-band fractional spur of -80dBc and a -145dBc reference spur. It comprises a conventional MASH $(\mathrm (D)\Delta \Sigma \mathrm (M))$ followed by a programmable Probability Mass Redistributor (PMR). The PMR requantizes the output of the $(\mathrm (D)\Delta \Sigma \mathrm (M))$ and redistributes its samples in such a way that the in-band spurs are reduced by 7dB compared to the $(\mathrm (D)\Delta \Sigma \mathrm (M))$ alone.
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16.9 4.48GHz 0.18μm SiGe BiCMOS精确频率分数n频率合成器,杂散音抑制产生-80dBc带内分数杂散
分数n锁相环反馈路径中的多模分频器的瞬时分频值由分频器控制器确定,该控制器通常实现为数字δ -sigma调制器$(\mathrm (D)\Delta \Sigma \mathrm (M))$。分数n锁相环的一个缺点是存在分数阶杂散,这是由$(\mathrm (D)\Delta \Sigma \mathrm (M))$引入的信号与环路中的非线性相互作用造成的。当频率接近整数边界的分数杂散位于环路带宽内时,它们不能通过滤波来衰减。连续要求器(SR)是基于$(\mathrm (D)\Delta \Sigma \mathrm (M))$的分频控制器的替代方案,它比$(\mathrm (D)\Delta \Sigma \mathrm (M))$更有效地随机化量化过程。Wang等人报道了2.4GHz电荷泵锁相环中-64dBc的最坏情况带内分数杂散[1]。Liang和Wang报道了在2GHz模拟锁相环中使用混合VCO和基于$(\mathrm (D)\Delta \Sigma \mathrm (M))$的分频控制器的-70dBc最坏情况分数杂散[2]。Familier和Galton通过实现高阶噪声整形改善了SR的性能。他们在具有三阶SR的3.3GHz模拟锁相环中实现了最坏情况下-72dBc的分数杂散[3]。SR每次量化一个位的频率控制字,因此,在n位模数的情况下,需要n级。Thirunarayanan等人使用四个SR量化块实现了混合MASH-SR分频控制器结构[4]。本文描述的分频控制器架构使4.48GHz模拟锁相环具有-80dBc的带内分数杂散和-145dBc的参考杂散。它包括一个传统的MASH $(\mathrm (D)\Delta \Sigma \mathrm (M))$和一个可编程的概率质量再分配器(PMR)。PMR要求$(\mathrm (D)\Delta \Sigma \mathrm (M))$的输出,并以这样一种方式重新分配其样本,与$(\mathrm (D)\Delta \Sigma \mathrm (M))$单独相比,带内杂散减少了7dB。
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