On using a 2-domain partitioned OBDD data structure in verification

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI:10.1109/HLDVT.2004.1431234

Tao Feng, Li-C. Wang, K. Cheng, Andy Lin

引用次数: 0

Abstract

In this paper, we propose a symbolic simulation method where Boolean functions can be efficiently manipulated through a 2-domain partitioned OBDD data structure. The functional partition is applied based on the key decision points in a circuit. We demonstrate that key decision points in an RTL model can be extracted automatically to facilitate verification at the gate level. The experiments show that the decision points can help to significantly reduce the OBDD size in both RTL and gate level circuit, solving problems that could not be solved with monolithic OBDD data structure. The performance of 2-domain partitioned OBDD approach is shown through the verification of several benchmark circuits.

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在验证中使用2域分区OBDD数据结构

在本文中，我们提出了一种符号模拟方法，该方法可以通过2域划分的OBDD数据结构有效地操作布尔函数。根据电路中的关键决策点进行功能划分。我们证明了RTL模型中的关键决策点可以自动提取，以促进门级的验证。实验表明，决策点可以显著减小RTL和门级电路中OBDD的尺寸，解决单片OBDD数据结构无法解决的问题。通过几个基准电路的验证，证明了二域分割OBDD方法的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)

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