Carrier-separated equivalent circuit modeling for steep subthreshold slope PN-body tied SOI FET

Abstract

In this paper, a new modeling approach for understanding and designing a recently proposed steep subthreshold slope SOI transistor (i.e. PN-Body Tied SOI FET [1-3]) is proposed. We revealed that the abrupt switching operation can be modeled using a simple equivalent circuit comprising two cross-coupled voltage inverters (i.e. electron current and hole current inverters). The model will be useful for designing PNBTFETs with optimum transition voltage, small hysteresis, and low standby current.