An integrated 80-V class-D power output stage with 94% efficiency in a 0.14µm SOI BCD process

Abstract

In this paper we present a highly-efficient 80V class-D power stage design in a 0.14μm SOI-based BCD process. Immunity to the on-chip supply bounce is realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and minimized switching loss are achieved with a 94% peak efficiency in the realized chip.