NEDA: a new distributed arithmetic architecture and its application to one dimensional discrete cosine transform

Abstract

Conventional Distributed Arithmetic (DA) is popular in ASIC design and it features on-chip ROM to achieve high speed and regularity. In this paper, a new DA architecture called NEDA is proposed aimed at reducing the cost metrics of power and area while maintaining high speed and accuracy in Digital Signal Processing (DSP) applications. Mathematical analysis proves that NEDA can implement inner product of vectors in the form of 2's complement numbers using only additions, followed by a small number of shifts at the final stage. Comparative study shows that NEDA outperforms widely-used approaches such as MAC and DA in many aspects. Being a high speed architecture free of ROM, multiplication and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. A hardware compression scheme is introduced to generate a butterfly structure with minimum number of additions. NEDA-based architecture for one dimensional DCT core is presented as an example.