Pub Date : 1999-12-01DOI: 10.1109/SIPS.1999.822348
J. Yen, Jiun-In Guo
In this paper, a new image encryption algorithm and its VLSI architecture are proposed. Based on a defined bit recirculation function and a binary sequence generated from a chaotic system, the gray level of each pixel in the image is transformed. The features of the algorithm are as follows: 1) low computational complexity, 2) high security, and 3) no distortion. In order to implement the system, its VLSI architecture with low hardware complexity, high computing speed, and high feasibility for VLSI implementation is also designed. Finally, two encrypted images are simulated and the fractal dimensions of the original and encrypted images are computed to demonstrate the effectiveness of the proposed algorithm.
{"title":"A new image encryption algorithm and its VLSI architecture","authors":"J. Yen, Jiun-In Guo","doi":"10.1109/SIPS.1999.822348","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822348","url":null,"abstract":"In this paper, a new image encryption algorithm and its VLSI architecture are proposed. Based on a defined bit recirculation function and a binary sequence generated from a chaotic system, the gray level of each pixel in the image is transformed. The features of the algorithm are as follows: 1) low computational complexity, 2) high security, and 3) no distortion. In order to implement the system, its VLSI architecture with low hardware complexity, high computing speed, and high feasibility for VLSI implementation is also designed. Finally, two encrypted images are simulated and the fractal dimensions of the original and encrypted images are computed to demonstrate the effectiveness of the proposed algorithm.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127418484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-12-01DOI: 10.1109/SIPS.1999.822381
M. Kuhlmann, K. Parhi
This paper presents a novel CORDIC algorithm and architecture for the rotation and vectoring mode in circular coordinate systems in which the directions of all micro-rotations are precomputed while maintaining a constant scale factor. Thus, an examination of the sign of the angle or y-remainder after each iteration is no longer required. By using Most-Significant Digit (MSD) first adder/multiplier, the critical path of the entire CORDIC architecture only requires (1.5 n+2) and (1.5 n+10) full-adders (n corresponds to the word-length of the inputs) for rotation and vectoring modes, respectively. This is a speed improvement of about 30% compared to the previously fastest reported shared rotation and vectoring mode implementations. Additionally, there is a higher degree of freedom in choosing the pipeline cutsets due to the novel independence of iteration i and i-1 in the CORDIC rotation. Optional pipelining can lead for example to an on-line delay of three clock-cycles where every clock cycles corresponds to a delay of twelve full-adders.
{"title":"A high-speed CORDIC algorithm and architecture for DSP applications","authors":"M. Kuhlmann, K. Parhi","doi":"10.1109/SIPS.1999.822381","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822381","url":null,"abstract":"This paper presents a novel CORDIC algorithm and architecture for the rotation and vectoring mode in circular coordinate systems in which the directions of all micro-rotations are precomputed while maintaining a constant scale factor. Thus, an examination of the sign of the angle or y-remainder after each iteration is no longer required. By using Most-Significant Digit (MSD) first adder/multiplier, the critical path of the entire CORDIC architecture only requires (1.5 n+2) and (1.5 n+10) full-adders (n corresponds to the word-length of the inputs) for rotation and vectoring modes, respectively. This is a speed improvement of about 30% compared to the previously fastest reported shared rotation and vectoring mode implementations. Additionally, there is a higher degree of freedom in choosing the pipeline cutsets due to the novel independence of iteration i and i-1 in the CORDIC rotation. Optional pipelining can lead for example to an on-line delay of three clock-cycles where every clock cycles corresponds to a delay of twelve full-adders.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133540591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-12-01DOI: 10.1109/SIPS.1999.822356
Zhongfeng Wang, Hiroshi Suzukit, K. Parhi
Finite precision effects on the performance of TURBO decoders have been analyzed and the optimal word lengths of variables have been determined considering tradeoffs between the performance and the hardware cost. It is shown that the performance degradation from the infinite precision is negligible if 4 bits are used for received bits and 6 bits for the extrinsic information. The state metrics normalization method suitable for TURBO decoders is also discussed. This method requires small amount of hardware and its speed does not depend on the number of states. Furthermore, we propose novel power-down techniques, which can achieve very high power-down efficiency without performance or latency degradation at the expense of negligible hardware overhead.
{"title":"VLSI implementation issues of TURBO decoder design for wireless applications","authors":"Zhongfeng Wang, Hiroshi Suzukit, K. Parhi","doi":"10.1109/SIPS.1999.822356","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822356","url":null,"abstract":"Finite precision effects on the performance of TURBO decoders have been analyzed and the optimal word lengths of variables have been determined considering tradeoffs between the performance and the hardware cost. It is shown that the performance degradation from the infinite precision is negligible if 4 bits are used for received bits and 6 bits for the extrinsic information. The state metrics normalization method suitable for TURBO decoders is also discussed. This method requires small amount of hardware and its speed does not depend on the number of states. Furthermore, we propose novel power-down techniques, which can achieve very high power-down efficiency without performance or latency degradation at the expense of negligible hardware overhead.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125426165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-12-01DOI: 10.1109/SIPS.1999.822371
Yun-Nan Chang, K. K. Parhi
This paper presents an efficient implementation of the pipeline FFT processor based on the radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By splitting the sequential input sample into parallel digit-serial data streams, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.
{"title":"Efficient FFT implementation using digit-serial arithmetic","authors":"Yun-Nan Chang, K. K. Parhi","doi":"10.1109/SIPS.1999.822371","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822371","url":null,"abstract":"This paper presents an efficient implementation of the pipeline FFT processor based on the radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By splitting the sequential input sample into parallel digit-serial data streams, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124539555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-12-01DOI: 10.1109/SIPS.1999.822317
Jiun-Lung Wang, Chung-Bin Wu, Bin-Da Liu, J. Yang
This paper discusses the recursive implementation of the discrete cosine transform (DCT) and its inverse (IDCT). The transform is constructed by using recursive filter structure to generate the transform kernel values. We first derive two trigonometric equations, which can be represented as the Chebyshev polynomial. Then we demonstrate that general length of the DCT and IDCT can be efficiently implemented by using the regressive structure derived from the recursive formulae. The computational complexity of each data throughput in these architectures is less than that in the conventional ones by as many as 50%. The proposed architectures are regular and suitable for parallel VLSI implementation.
{"title":"Implementation of the discrete cosine transform and its inverse by recursive structures","authors":"Jiun-Lung Wang, Chung-Bin Wu, Bin-Da Liu, J. Yang","doi":"10.1109/SIPS.1999.822317","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822317","url":null,"abstract":"This paper discusses the recursive implementation of the discrete cosine transform (DCT) and its inverse (IDCT). The transform is constructed by using recursive filter structure to generate the transform kernel values. We first derive two trigonometric equations, which can be represented as the Chebyshev polynomial. Then we demonstrate that general length of the DCT and IDCT can be efficiently implemented by using the regressive structure derived from the recursive formulae. The computational complexity of each data throughput in these architectures is less than that in the conventional ones by as many as 50%. The proposed architectures are regular and suitable for parallel VLSI implementation.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128187651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822315
Jae-Yong Kim, Sung-Bong Yang
Many suboptimal motion vector search algorithms have been proposed because the full search algorithm, which is an optimal method, requires huge computational requirements. These algorithms find motion vectors simply from the center of the search window. In this paper we propose an efficient motion vector search algorithm (GLS), which exploits the global motion information obtained from the previous three frames and the local motion information regarding the motion vectors of the neighboring blocks of the current block in order to predict the initial search point. GLS searches for a motion vector from this initial search point, instead of the center of the search window, using either the diamond search algorithm (DS) or the unrestricted small diamond search algorithm (USDS) which performs its search always with a smaller diamond search pattern. USDS has the same search pattern as that of the last search step in DS. Experimental results show that GLS is a faster and more accurate motion vector search method than other suboptimal methods.
{"title":"An efficient search algorithm for BLOCK motion estimation","authors":"Jae-Yong Kim, Sung-Bong Yang","doi":"10.1109/SIPS.1999.822315","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822315","url":null,"abstract":"Many suboptimal motion vector search algorithms have been proposed because the full search algorithm, which is an optimal method, requires huge computational requirements. These algorithms find motion vectors simply from the center of the search window. In this paper we propose an efficient motion vector search algorithm (GLS), which exploits the global motion information obtained from the previous three frames and the local motion information regarding the motion vectors of the neighboring blocks of the current block in order to predict the initial search point. GLS searches for a motion vector from this initial search point, instead of the center of the search window, using either the diamond search algorithm (DS) or the unrestricted small diamond search algorithm (USDS) which performs its search always with a smaller diamond search pattern. USDS has the same search pattern as that of the last search step in DS. Experimental results show that GLS is a faster and more accurate motion vector search method than other suboptimal methods.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114323537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822344
C. Shih, N. Sherkat, P. Thomas
During the last few years automating lace handling has received much attention in the United Kingdom. Research and development is ongoing in the two main areas of automatic lace cutting and automatic lace quality inspection. This paper reports on research and development work under gone at the Nottingham Trent University, in collaboration with local industry, in automation of lace scalloping. The research is reviewed in its various stages of development. Three different methods together with their associated experimental results are described and the merits of each are discussed. An innovative approach, based on neural fuzzy logic, for dealing with the problem of lace distortion, due to its flexible nature, is described.
{"title":"A real-time vision based automatic lace trimming process","authors":"C. Shih, N. Sherkat, P. Thomas","doi":"10.1109/SIPS.1999.822344","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822344","url":null,"abstract":"During the last few years automating lace handling has received much attention in the United Kingdom. Research and development is ongoing in the two main areas of automatic lace cutting and automatic lace quality inspection. This paper reports on research and development work under gone at the Nottingham Trent University, in collaboration with local industry, in automation of lace scalloping. The research is reviewed in its various stages of development. Three different methods together with their associated experimental results are described and the merits of each are discussed. An innovative approach, based on neural fuzzy logic, for dealing with the problem of lace distortion, due to its flexible nature, is described.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"14 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127102466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822357
Chung-Wei Ku, Fu-Yen Kuo, Chi-Kuang Chen, Liang-Gee Chen
This paper discusses the design, implementation, and performance evaluation of a low powered correlator architecture for multi-code CDMA systems. In CDMA systems, correlators are used to de-spread the received signals and are important blocks for RAKE receivers. We proposed a low powered correlator architecture to de-spread input with several PN sequence concurrently, According to our preliminary simulation results, the suggested architecture can de-spread the input signal with two PN codes simultaneously and save 41% power consumption compared with traditional correlator architecture.
{"title":"Low power strategy about correlator array for CDMA baseband processor","authors":"Chung-Wei Ku, Fu-Yen Kuo, Chi-Kuang Chen, Liang-Gee Chen","doi":"10.1109/SIPS.1999.822357","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822357","url":null,"abstract":"This paper discusses the design, implementation, and performance evaluation of a low powered correlator architecture for multi-code CDMA systems. In CDMA systems, correlators are used to de-spread the received signals and are important blocks for RAKE receivers. We proposed a low powered correlator architecture to de-spread input with several PN sequence concurrently, According to our preliminary simulation results, the suggested architecture can de-spread the input signal with two PN codes simultaneously and save 41% power consumption compared with traditional correlator architecture.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132162635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822353
M. Goel, S. Appadwedula, N.R. Shambhag, K. Ramchandran, D.L. Jones
A low-power multimedia communication system is proposed. Power reductions are achieved by employing dynamic algorithm transforms and joint source-channel coding to reconfigure the system in the presence of variabilities in source and channel data. Configuration parameters are source rate, error correction capability of the channel encoder/decoder, number of powered-up fingers in the RAKE receiver and transmit power of the power amplifier. Energy-optimum configurations are obtained by minimizing energy consumption under the constraints of end-to-end distortion and total transmission rate. The proposed system is tested over a variety of images, distances (ranging from 2 to 100 meters) and multipath channels. Simulation results using 0.18 /spl mu/m, 2.5 V CMOS parameters show that the reconfigurable system can achieve average energy savings of 59% as compared to a fixed system designed for the worst case. Also, the proposed system consumes 16% less energy as compared to a transmit-power-controlled system.
提出了一种低功耗多媒体通信系统。通过采用动态算法变换和联合源信道编码，在源信道数据存在可变性的情况下重新配置系统，实现了功耗降低。配置参数为信源速率、信道编码器/解码器的纠错能力、RAKE接收机上电手指数和功率放大器的发射功率。在端到端失真和总传输速率约束下，通过最小化能量消耗获得能量最优配置。该系统在各种图像、距离(从2米到100米)和多径信道上进行了测试。使用0.18 /spl mu/m, 2.5 V CMOS参数的仿真结果表明，与针对最坏情况设计的固定系统相比，可重构系统可实现59%的平均节能。此外，与传输功率控制系统相比，所提出的系统消耗的能量少16%。
{"title":"A low-power multimedia communication system for indoor wireless applications","authors":"M. Goel, S. Appadwedula, N.R. Shambhag, K. Ramchandran, D.L. Jones","doi":"10.1109/SIPS.1999.822353","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822353","url":null,"abstract":"A low-power multimedia communication system is proposed. Power reductions are achieved by employing dynamic algorithm transforms and joint source-channel coding to reconfigure the system in the presence of variabilities in source and channel data. Configuration parameters are source rate, error correction capability of the channel encoder/decoder, number of powered-up fingers in the RAKE receiver and transmit power of the power amplifier. Energy-optimum configurations are obtained by minimizing energy consumption under the constraints of end-to-end distortion and total transmission rate. The proposed system is tested over a variety of images, distances (ranging from 2 to 100 meters) and multipath channels. Simulation results using 0.18 /spl mu/m, 2.5 V CMOS parameters show that the reconfigurable system can achieve average energy savings of 59% as compared to a fixed system designed for the worst case. Also, the proposed system consumes 16% less energy as compared to a transmit-power-controlled system.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"311 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131703661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822369
T. Tung, K. Yao, D. Chen, R. E. Hudson, C. Reed
We propose a 2-D beamforming system that is designed for multiple source localization, signal enhancement, interference suppression, and noise reduction. The 2-D locations of the sources can be estimated by the wideband MUSIC algorithm. After estimating the locations of the sources, the maximum power beamforming algorithm is applied to enhance the desired signal and attenuate undesired spatially distributed interferences and background noises. Performance gains from simulations and experiments are shown to be promising for multimedia applications.
{"title":"Source localization and spatial filtering using wideband MUSIC and maximum power beamforming for multimedia applications","authors":"T. Tung, K. Yao, D. Chen, R. E. Hudson, C. Reed","doi":"10.1109/SIPS.1999.822369","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822369","url":null,"abstract":"We propose a 2-D beamforming system that is designed for multiple source localization, signal enhancement, interference suppression, and noise reduction. The 2-D locations of the sources can be estimated by the wideband MUSIC algorithm. After estimating the locations of the sources, the maximum power beamforming algorithm is applied to enhance the desired signal and attenuate undesired spatially distributed interferences and background noises. Performance gains from simulations and experiments are shown to be promising for multimedia applications.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":" 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114051235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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