{"title":"Input and Output Generation for the Verification of ALU: A Use Case","authors":"Ondrej Cekan, R. Panek, Z. Kotásek","doi":"10.1109/EWDTS.2018.8524641","DOIUrl":null,"url":null,"abstract":"The paper presents the approach to universal stimuli generation for an arithmetic-logic unit (ALU). It is not focused only on input data generation, but it is possible to generate also expected output in one stimulus. The process of generation is based on a probabilistic constrained grammar which is designed to universally describe stimuli for various circuits. This grammar is processed by our framework. The experiment in functional verification, which shows the quality of generated stimuli, is also presented.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"266 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2018.8524641","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The paper presents the approach to universal stimuli generation for an arithmetic-logic unit (ALU). It is not focused only on input data generation, but it is possible to generate also expected output in one stimulus. The process of generation is based on a probabilistic constrained grammar which is designed to universally describe stimuli for various circuits. This grammar is processed by our framework. The experiment in functional verification, which shows the quality of generated stimuli, is also presented.
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