Optimization and benchmarking of graphene-based heterostructure FETs

Abstract

We compare the performance prospects of three recently proposed and demonstrated transistors based on vertical and lateral graphene-based heterostructures, with the requirements of the International Technology Roadmap for Semiconductors. All devices provide large Ion/Ioff ratios, but only the lateral heterostructure field-effect transistors exhibit promising dynamic figures of merit, i.e. delay time and power-delay-product. The assessment is based on numerical simulations using our in-house nanoscale device simulation tool NanoTCAD Vides.