Thermal effects of TSV (through silicon via) with void

Abstract

Duo to the TSV fabrication process, the void or stream often exists in the TSV. As we all know the void and stream cannot easily being avoided, the thermal mechanical reliability of TSV integrated circuit (IC) shall be studied deeply for evaluating the fatigue life of the IC products and rearranging the location of TSVs to relieving thermal issues. In addition, the thermal mechanism of void model is different from the vertical TSV. Therefore, it is meaningful and significant to study the thermal stability of void model. This paper evaluates the thermal mechanical stability during the change of the void location and size by finite element method (FEM). The interfacial lines of void TSV suffer different thermal stress and strain induced by the unbalanced deformation of the void, and the interaction of void and TSV.