B. Sell, B. Bigwood, S. Cha, Z. Chen, P. Dhage, P. Fan, M. Giraud-Carrier, A. Kar, E. Karl, C. Ku, R. Kumar, T. Lajoie, H. Lee, G. Liu, S. Liu, Y. Ma, S. Mudanai, L. Nguyen, L. Paulson, K. Phoa, K. Pierce, A. Roy, R. Russell, J. Sandford, J. Stoeger, N. Stojanovic, A. Sultana, J. Waldemer, J. Wan, W. Xu, D. Young, J. Zhang, Y. Zhang, P. Bai
{"title":"22FFL: A high performance and ultra low power FinFET technology for mobile and RF applications","authors":"B. Sell, B. Bigwood, S. Cha, Z. Chen, P. Dhage, P. Fan, M. Giraud-Carrier, A. Kar, E. Karl, C. Ku, R. Kumar, T. Lajoie, H. Lee, G. Liu, S. Liu, Y. Ma, S. Mudanai, L. Nguyen, L. Paulson, K. Phoa, K. Pierce, A. Roy, R. Russell, J. Sandford, J. Stoeger, N. Stojanovic, A. Sultana, J. Waldemer, J. Wan, W. Xu, D. Young, J. Zhang, Y. Zhang, P. Bai","doi":"10.1109/IEDM.2017.8268475","DOIUrl":null,"url":null,"abstract":"A FinFET technology named 22FFL has been developed that combines high-performance, ultra-low power logic and RF transistors as well as single-pattern backend flow for the first time. High performance transistors exhibit 57%/87% higher NMOS/PMOS drive current compared to the previously reported 22nm technology [1]. New ultra-low power logic devices are introduced that reduce bit cell leakage by 28x compared to a regular SRAM cell enabling a new 6T low-leakage SRAM with bit cell leakage of sub 1pA/cell. An RF device with optimized layout has been developed and shows excellent fT/fMAX of (230GHz/284GHz) and (238GHz/242GHz) for NMOS and PMOS respectively.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"57","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2017.8268475","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 57
Abstract
A FinFET technology named 22FFL has been developed that combines high-performance, ultra-low power logic and RF transistors as well as single-pattern backend flow for the first time. High performance transistors exhibit 57%/87% higher NMOS/PMOS drive current compared to the previously reported 22nm technology [1]. New ultra-low power logic devices are introduced that reduce bit cell leakage by 28x compared to a regular SRAM cell enabling a new 6T low-leakage SRAM with bit cell leakage of sub 1pA/cell. An RF device with optimized layout has been developed and shows excellent fT/fMAX of (230GHz/284GHz) and (238GHz/242GHz) for NMOS and PMOS respectively.
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