Design and implementation of a 1-bit FinFET Full Adder cell for ALU in subthreshold region

Abstract

The FinFET based Full Adder in various cell designs is investigated in terms of performance and energy efficiency. Additionally, the performance of the FinFET Full Adder in the subthreshold region reveals significant results in low power technology. The 1-bit FinFET based Full Adder is designed in four different cell designs, and while the average power dissipated, delays, power-delay-product (PDP) and energy-delay-product (EDP) of all four topologies were analyzed based on the types of transistors used i.e. conventional Field Oxide Transistor (MOSFET) and FinFET. Based on this study, FinFET based Full Adder shows an average of 94 % reduction in delay, 97 % reduction in power dissipation and 99 % reduction for both PDP and EDP over the conventional FET, giving FinFET advantages in energy efficiency.