NOCBENCH: NOC synthesis benchmarks

Abstract

ITRS Semiconductor roadmap projects that hundreds of processors will be needed for future generation system on chip (SOC) designs. Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Among the NoC conception problems, there exists the Network-on-Chip Topology synthesis Problem, which consists in generating the topology of the NoC to guarantee the system performance, silicone area and power consumption design objective. The typical and well adapted design methodologies in the literature all take a core graph as the input of NoC synthesis, which represents the communication between components. But until now there are no common NoC synthesis benchmarks to test the different methods over the same instances. In this paper, a core graph generator and a suit of generated core graphs are proposed to give researcher a common standard NoC synthesis benchmarks. This core graph generator and benchmarks can help and accelerate the NoC synthesis research of large scale SoC design.