Failure Analysis for SIP IC after TC reliability test

Abstract

A System-In-Package (SIP) chip failed after 240 cycle temperature cycle test. Electrical test results suggested that the failure was due to an open circuit. . This SIP chip was built with a three layers structure. The upper and lower modules are interconnected through an interposer die. Based solely on the ATE results, the faulty cell could not be located. . Use of standard analysis techniques such as 3D X-ray imaging and Confocal Scanning Acoustic Microscopy (CSAM) was not enough to localize the defect. The fault location was isolated by laser decapsulation and probing, and the open circuit was confirmed to be in the interposer die. Use of parallel grinding was a key enabler to succeed in this analysis. From this, a new workflow was developed for fault isolation in SIP IC. The gradual reduction in candidate locations for the failure root cause was decisive in this analysis.