Non-intrusive FPGA-based profiler for loop execution characterization

Abstract

Embedded system design involves meeting strict design goals such as performance, area and power consumption. In-order to meet these design goals embedded systems are implemented in programmable processors and application-specific hardware. Hardware/Software partitioning is thus, a critical step in the realization of embedded systems. The initial software description of the application is profiled to identify the critical sections of the software code which consume the largest percentage of execution time. These critical sections are then chosen as ideal candidates to be implemented as application specific hardware. It is reported that 90 percent of the execution time is spent in executing loops in typical embedded systems applications. In this paper we present a non-intrusive, low overhead FPGA based hardware profiler to identify at run-time the different loops and the time taken to execute these loops from the execution of different scenarios of the application software when compiled on the chosen programmable processor.